Dual Logic Circuit Layout for Fault Attack Detection
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Solution Overview
Problem
The duplication approach in digital circuits is vulnerable to fault attacks since identical circuits make it easy for attackers to identify and inject errors in both the original and duplicate circuits, leading to undetectable errors.
Innovation Solution
Implementing a dual circuit with inverted outputs for the duplicate circuit, where errors are injected in an inverted manner, and using input and output delay elements to align signals for comparison, making it harder for attackers to coordinate attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identical duplicate circuits are used for error detection, then all errors in one circuit are detected, but the same error in both circuits cannot be detected
Solution Approach 1:
The patent applies asymmetry by using dual circuits with inverted logic instead of identical duplicate circuits. The dual circuit has inverted inputs and outputs compared to the original circuit, creating an asymmetric structure that prevents attackers from easily identifying corresponding locations to inject the same error in both circuits.
Solution Approach 2:
The patent uses inversion by creating a dual circuit where all logic gates are inverted (AND becomes OR, OR becomes AND, NAND becomes NOR, etc.). This inversion makes it difficult for attackers to coordinate errors because the same physical location in the dual circuit corresponds to a different logical function, requiring the attacker to understand and exploit the inverted logic relationships.
2Device complexity
If the original circuit and duplicate circuit are fully identical, then error detection is simplified, but attackers can easily identify locations to inject errors
Solution Approach 1:
The patent creates asymmetry between the original and dual circuits by inverting the logic gates and signal polarities. This asymmetric structure makes it difficult for attackers to identify corresponding injection points because the physical layout may be similar but the logical functions are inverted, requiring complex analysis to match corresponding locations.
3Object-affected harmful factors
If delay elements are added to misalign signals, then coordination of errors becomes harder, but circuit complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-inverting the inputs and outputs of the dual circuit before comparison. This preliminary inversion is built into the circuit structure itself, eliminating the need for additional delay elements or complex timing mechanisms to prevent error coordination. The inversion is performed as part of the normal circuit operation.
Data Source
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AI summary
Various embodiments relate to a circuit system, including: an original circuit; a dual circuit, wherein the dual circuit is a dual of the original circuit; an input inverter connected the dual circuit, wherein the input inverter inverts system inputs; an output inverter connected to one of the original circuit and the dual circuit, wherein the output inverter inverts the output of the connected original circuit or dual circuit; and a comparator receiving and comparing the output of the invertor and the output of one of the original circuit and the dual circuit not connected to the inverter, wherein the comparator indicates an error when the received outputs are not identical and indicating no error when the received outputs are identical.