Dual-Loop CDR Clock Recovery for Adaptation Error and Jitter Filtering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In clock data recovery circuitry, the adaptation of the feed-forward equalizer in the data recovery loop can cause errors in the clock recovery loop, limiting the performance of both loops due to interference and jitter issues.
Innovation Solution
A dual clock recovery loop system is implemented, where a first clock recovery loop operates on equalized data to provide a first timing error signal, and a second clock recovery loop operates on unequalized data to provide a second timing error signal, with combining circuitry that filters out low-frequency adaptation errors and high-frequency jitter, using oscillator circuitry to derive a recovered clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single clock recovery loop operates on equalized data, then the clock recovery can adapt to channel conditions, but adaptation errors from the data recovery loop degrade clock recovery performance
Solution Approach 1:
The patent divides the clock recovery function into two separate loops: a first clock recovery loop that operates on equalized data and a second clock recovery loop that operates on unequalized data. This segmentation isolates the harmful adaptation errors from the second loop, allowing it to provide a clean timing error signal without being corrupted by data recovery loop adaptations.
Solution Approach 2:
The patent introduces combining circuitry as an intermediary that merges the timing error signals from both clock recovery loops. This intermediary component intelligently combines the advantages of both loops while filtering out the harmful adaptation errors, producing a cleaned timing error signal for clock recovery.
2Reliability
If a dual clock recovery loop is implemented, then adaptation errors are filtered out, but the device complexity increases
Solution Approach 1:
The patent merges the functionality of two clock recovery loops with a combining circuitry that integrates their outputs. By combining the loops in this specific manner, the patent achieves error filtering while maintaining a unified clock recovery function, reducing the practical complexity increase compared to implementing completely separate systems.
3Measurement precision
If the feed-forward equalizer is adaptively adjusted, then data recovery performance improves, but timing errors are introduced in the clock recovery loop
Solution Approach 1:
The patent segments the timing error signal sources by creating two separate clock recovery loops. The second loop operating on unequalized data provides a timing error signal that is isolated from FFE adaptation effects, while the first loop captures the adapted timing information. This segmentation allows data recovery to benefit from FFE adaptation while clock recovery uses the clean signal from the second loop.
Solution Approach 2:
The patent converts the harmful effect of FFE adaptation on clock recovery into a benefit by using the first clock recovery loop to capture the adapted timing characteristics. The combining circuitry then merges this adapted timing information with the clean timing error from the second loop, effectively using the adaptation errors in a controlled manner to improve overall system performance.
Data Source
AI summary
A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.