Dual-Loop Charge Pump Circuit for Low-Power Reliable PLLs
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Solution Overview
Problem
Existing PLL circuits and charge pump circuits consume significant power and face challenges in reducing electro-migration risks and self-heating, especially in high-speed data communication applications.
Innovation Solution
The enhanced PLL circuit and charge pump circuit incorporate a dual loop control mechanism with an H-bridge circuit, utilizing a single sense operational amplifier and a common mode operational amplifier to reduce power consumption and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional charge pump circuits with multiple sense operational amplifiers and push-pull output stages are used, then clock generation performance is maintained, but power consumption increases significantly
Solution Approach 1:
The patent extracts and removes unnecessary components from the conventional charge pump circuit. Specifically, it eliminates one sense operational amplifier and the push-pull output stage, retaining only the essential H-bridge circuitry and a single sense operational amplifier. This extraction of non-essential components directly reduces power consumption while preserving the core charge pump functionality needed for reliable clock generation.
Solution Approach 2:
The patent replaces complex, high-power operational amplifiers with simpler, lower-power alternatives. The simplified operational amplifier design consumes less power and can be implemented with fewer transistors, effectively using a 'simpler' version that achieves the same functional goal with reduced resource consumption.
2Power
If higher voltage domains are used for charge pump operation, then sufficient drive current is achieved, but electro-migration risk increases
Solution Approach 1:
The patent changes the voltage domain parameter by implementing the charge pump circuit in a lower voltage domain (1.8V instead of higher voltages). This parameter change maintains sufficient drive current through optimized circuit topology and transistor sizing, while simultaneously reducing the electro-migration risk that increases with higher voltage operation.
3Speed
If complex analog circuitry is incorporated in PLL circuits, then high-speed clock generation capability is achieved, but power consumption and heat generation increase
Solution Approach 1:
The patent segments the PLL circuit into distinct functional blocks with optimized power consumption characteristics. The charge pump portion is separated and simplified independently from the rest of the PLL, allowing high-speed operation where needed while reducing power consumption in the charge pump segment that directly impacts overall power usage and heat generation.
Data Source
AI summary
Embodiments of the present disclosure provide an enhanced phase-locked loop (PLL) circuit and an enhanced charge pump circuit used for various applications, including high-speed data clock generation for complex integrated circuit (IC) designs. The disclosed PLL circuit and charge pump circuit enable significant power and supply current reduction, improved circuit reliability; reduced self-heating and electro-migration risk, and enable use of lower power operational amplifiers with the operational amplifiers driving high impedance nodes.