Dual-Loop Clock Recovery With Adaptive Thresholds for Pattern Lock
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Solution Overview
Problem
High-speed serial links face challenges in timing recovery, particularly in power consumption, silicon area, and design complexity, with existing techniques losing frequency lock when encountering specific data patterns and requiring additional clock phases and slicers.
Innovation Solution
A clock recovery circuit and method utilizing a dual loop clock recovery system with a data slicer, error blocks, and a voltage-controlled oscillator, which adapts threshold voltage and sampling phase based on bit patterns to maintain frequency lock and optimize phase adjustment, reducing power and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional clock phases and slicers are used to maintain frequency lock across all data patterns, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a dynamic threshold voltage adjustment mechanism where the threshold voltage is adaptively modified based on detected data patterns. This allows a single slicer to dynamically adapt its decision boundary to maintain frequency lock across different data patterns, replacing the need for multiple static slicers configured for different patterns.
Solution Approach 2:
The system changes the threshold voltage parameter in response to detected data patterns. By monitoring the data pattern and adjusting the threshold voltage accordingly, the system maintains accurate sampling and frequency lock using a single slicer, rather than requiring multiple slicers with fixed thresholds for different patterns.
2Adaptability or versatility
If multiple error blocks are used to handle different data patterns, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent makes a single error block universal by enabling it to handle multiple different data patterns through dynamic threshold voltage adjustment. The error block adapts its operation based on the detected pattern, allowing one error block to perform the function of multiple dedicated error blocks would otherwise be needed.
Solution Approach 2:
The error block performs self-adaptation by monitoring the data pattern and automatically adjusting the threshold voltage through feedback mechanisms. This self-service capability allows the error block to optimize its performance for different patterns without requiring external control or multiple dedicated blocks for each pattern.
3Measurement precision
If threshold voltage is dynamically adjusted based on data patterns, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the detected data pattern is fed back to the voltage threshold modification circuitry, which then adjusts the threshold voltage accordingly. This closed-loop feedback system continuously optimizes the sampling threshold based on the current data pattern, improving measurement precision while using a relatively simple adjustment circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves quick frequency lock across various data patterns, including repeating clock patterns, with reduced power consumption and design complexity, achieving a locking range of 500,000 ppm and low inter-symbol interference jitter.
Implementation Method 1
a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator
Data Source
AI summary
A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.