Dual-Loop Clock Data Recovery for Drift-Stable High-Speed Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock data recovery circuits experience frequency drift when no data signal is received, and replacing the analog loop filter with a digital one improves frequency stability but reduces loop response speed, making them unsuitable for high-frequency applications.
Innovation Solution
A clock data recovery circuit design incorporating a first detecting circuit, a digital loop filter, a control voltage generating circuit, a voltage-controlled oscillator, a phase adjustment circuit, and a frequency divider, which allows for simultaneous operation of two loops to stabilize the sampling clock signal and enhance loop response speed without additional switching circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an analog loop filter is used in the clock data recovery circuit, then the circuit structure is simple, but frequency drift occurs when no data signal is received for a certain period
Solution Approach 1:
The patent divides the loop filter function into two separate circuits: a first loop filter for phase detection and a second loop filter for frequency detection. This segmentation allows each filter to specialize in its respective function, with the second loop filter specifically addressing frequency drift by continuously monitoring and adjusting frequency even when data signals are absent.
Solution Approach 2:
The patent introduces a frequency detector as an intermediary component that continuously monitors the frequency of the sampling clock signal and generates adjustment signals to prevent frequency drift. This intermediary mechanism bridges the gap between the phase-locked loop and frequency stability, ensuring reliable operation during data signal absence.
2Reliability
If the analog loop filter is replaced with a digital loop filter to reduce frequency drift, then frequency stability is improved, but the loop response speed becomes insufficient
Solution Approach 1:
The patent applies different filter characteristics to different functional requirements: the first loop filter uses analog components optimized for fast phase response, while the second loop filter uses digital components optimized for accurate frequency detection. This local quality differentiation allows the system to achieve both fast response speed and high frequency stability simultaneously.
Solution Approach 2:
By separating phase detection and frequency detection into independent loops with specialized filters, the system allows the phase-locked loop to respond quickly to phase changes while the frequency-locked loop ensures long-term frequency stability, resolving the speed-stability tradeoff.
3Speed
If a digital loop filter is used to support higher data signal frequencies, then the loop response speed must be increased, but this complicates the circuit design
Solution Approach 1:
The patent replaces complex digital signal processing mechanisms with a hybrid analog-digital approach. The analog first loop filter handles fast phase tracking with simple RC circuits, while the digital second loop filter handles frequency detection with straightforward counting logic, avoiding the need for complex high-speed digital filters.
Data Source
AI summary
A clock data recovery circuit includes: a first detecting circuit for detecting phases of an incoming data signal and a sampling clock signal to generate a first detection signal; a loop filter for generating a control signal according to the first detection signal; a second detecting circuit for detecting phases of a reference signal and a feedback signal to generate a second detection signal; a control voltage generating circuit for generating a control voltage based on the second detection signal; a voltage-controlled oscillator for generating the sampling clock signal according to the control voltage; a phase adjustment circuit for adjusting the phase of the sampling clock signal according to the control signal to generate the phase-adjusted signal; and a frequency divider circuit for conducting a frequency division operation on the phase-adjusted signal to generate the feedback signal.