Dual-Loop Clock Recovery Circuit for Fast Lock and Low Phase Jitter
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Solution Overview
Problem
High-speed serial communication links in integrated circuits face challenges in achieving efficient clock and data recovery, particularly in acquiring frequency and phase locks quickly while minimizing power consumption and phase jitter.
Innovation Solution
A dual-loop sequential clock recovery circuit with a bang-bang phase detection circuit, featuring a frequency tracking loop, phase tracking loop, and a voltage-controlled oscillator, where a programmable delay element and switchable resistor are used to optimize loop gain and reduce power consumption by enabling sequential frequency and phase lock acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a dual-loop sequential clock recovery circuit is used to rapidly acquire frequency and phase locks, then the locking time is reduced, but the circuit complexity increases
Solution Approach 1:
The clock recovery circuit is divided into two sequential loops: a frequency tracking loop that first acquires frequency lock, and then a phase tracking loop that acquires phase lock. This segmentation allows the complex dual-loop functionality to be implemented in a structured manner, reducing the overall locking time while managing circuit complexity through modular design
Solution Approach 2:
The circuit dynamically switches between different operating modes using a lock detector and control logic. The frequency tracking loop operates first, and upon detecting frequency lock, the system transitions to the phase tracking loop. This dynamic operation optimizes the locking process by activating only the necessary loop at each stage, reducing effective circuit complexity during operation
2Device complexity
If a bang-bang phase detection circuit is used in the phase tracking loop, then the circuit simplicity is improved, but the phase jitter increases
Solution Approach 1:
The loop filter acts as an intermediary between the bang-bang phase detector and the voltage-controlled oscillator. It processes the coarse phase error signals from the bang-bang detector and generates smooth control voltages, thereby reducing phase jitter while maintaining the simplicity of the bang-bang detection approach
Solution Approach 2:
The loop filter parameters (resistor and capacitor values) are optimized to achieve the desired balance between circuit simplicity and phase jitter reduction. By carefully selecting these parameters, the system maintains the simplicity of the bang-bang detector while the filter characteristics suppress high-frequency noise and reduce phase jitter
3Reliability
If the loop gain is increased to reduce phase jitter, then the phase jitter is reduced, but the power consumption increases
Solution Approach 1:
The circuit operates in periodic stages: first the frequency tracking loop acquires frequency lock, then the phase tracking loop acquires phase lock. During each stage, only the necessary components are fully active, reducing overall power consumption while still achieving low phase jitter during the final locked state
Solution Approach 2:
The loop gain parameters are optimized to achieve the minimum necessary gain to reduce phase jitter to acceptable levels. The lock detector and control logic adjust the operating state based on lock status, reducing power consumption when full gain is not required while maintaining low phase jitter during locked operation
4Speed
If a frequency tracking loop is added before the phase tracking loop, then the frequency acquisition speed is improved, but the device complexity increases
Solution Approach 1:
The frequency tracking loop is segmented as a separate, dedicated stage before the phase tracking loop. This segmentation allows rapid frequency acquisition through specialized frequency detection and correction circuitry, while the phase tracking loop handles phase alignment. The modular segmentation manages complexity by dividing functions into distinct, manageable blocks
Solution Approach 2:
The frequency tracking loop performs preliminary frequency acquisition and correction before the phase tracking loop begins operation. By pre-establishing frequency lock, the system prepares the signal for subsequent phase locking, thereby improving overall frequency acquisition speed while managing complexity through sequential operation
Data Source
AI summary
A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.