Dual-Loop Clock Recovery Circuit for Jitter-Tolerant Phase Locking
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Solution Overview
Problem
High-speed digital communication systems face challenges in synchronizing clock signals with data intervals, leading to data loss or misinterpretation due to synchronization issues, especially in modern protocols like PCI Express, SONET, and InfiniBand where data intervals are nanoseconds or less in duration.
Innovation Solution
A clock recovery circuit utilizing a delay lock loop with two phase shifters and phase detectors, one digital and one analog, to accurately synchronize the clock signal with the data signal by adjusting the phase shift over an infinite range, compensating for frequency differences and jitter, and providing a recovered clock signal that matches the data signal's phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data intervals are shortened to increase communication speed, then productivity is improved, but measurement precision of synchronization deteriorates
Solution Approach 1:
The synchronization system is divided into two independent loops: a digital loop for coarse frequency adjustment and an analog loop for fine phase synchronization. This segmentation allows each loop to specialize in different aspects of synchronization, enabling the system to achieve both high speed adaptation and precise timing alignment required for shortened data intervals.
Solution Approach 2:
The system dynamically switches between digital and analog control mechanisms based on synchronization requirements. The digital loop provides rapid frequency acquisition while the analog loop continuously refines phase alignment, creating a dynamic adaptation capability that maintains precision even as data intervals shrink to nanosecond durations.
2Device complexity
If a single loop synchronization system is used, then device complexity is reduced, but reliability of synchronization deteriorates
Solution Approach 1:
The synchronization function is segmented into two separate loops with distinct roles: the digital loop handles frequency acquisition and coarse synchronization, while the analog loop handles fine phase adjustment. This segmentation improves reliability by providing redundant synchronization mechanisms that can operate independently or in combination.
Solution Approach 2:
The phase detector serves as an intermediary element that bridges the digital and analog loops, comparing the recovered clock signal with the incoming data signal and generating error signals for both loops. This intermediary mechanism ensures coordinated operation between the two loops, enhancing overall synchronization reliability.
3Device complexity
If phase shift range is limited, then device complexity is reduced, but adaptability to frequency differences deteriorates
Solution Approach 1:
The phase adjustment function is segmented between two shifters: the digital phase shifter provides coarse frequency adjustment over a wide range, while the analog phase shifter provides fine-tuned phase adjustment. This segmentation enables the system to accommodate large frequency differences without requiring a single complex phase shifter with unlimited adjustment range.
Solution Approach 2:
The system dynamically allocates adjustment range between the two phase shifters based on the magnitude of frequency deviation. When large frequency differences exist, the digital loop provides the primary adjustment; when frequency is close, the analog loop provides precise alignment. This dynamic allocation maintains adaptability while simplifying individual shifter designs.
Data Source
AI summary
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.