Dual-Loop Clock Recovery for Pattern-Adaptable Serial Link Timing
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Solution Overview
Problem
High-speed serial links face challenges in timing recovery, particularly in power consumption, silicon area, and design complexity, with existing techniques losing frequency lock when encountering specific data patterns and requiring additional clock phases and slicers.
Innovation Solution
A clock recovery circuit and method utilizing a dual loop clock recovery system with a data slicer, error blocks, and a voltage-controlled oscillator, which selectively outputs error signals based on data patterns to adjust the threshold voltage and sampling phase, optimizing power and area efficiency while maintaining frequency lock across various patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional clock phases and slicers are used to maintain frequency lock across all data patterns, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a dynamic dual-loop clock recovery system where the first loop handles frequency acquisition and the second loop handles phase adjustment. The system adaptively switches between different error signal generation modes based on data patterns, allowing a single clock phase to maintain frequency lock across all patterns including challenging sequences like 1010.
Solution Approach 2:
The clock recovery function is segmented into two independent loops: the first loop (frequency acquisition loop) uses one error signal generation mode, while the second loop (phase adjustment loop) uses another mode. This segmentation allows each loop to be optimized for its specific function, enabling reliable frequency lock without requiring multiple clock phases.
2Productivity
If high-speed serial link interface speed is increased to transmit more data, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters of the clock recovery circuit by implementing pattern-adaptable error signal generation. By selectively outputting different error signals based on detected data patterns, the circuit optimizes its operation at high speeds while minimizing unnecessary switching and power consumption, enabling reliable operation at 112 Gbps and above.
3Productivity
If high-speed serial link interface speed is increased to transmit more data, then productivity is improved, but silicon area increases
Solution Approach 1:
The dual-loop clock recovery system is designed to perform multiple functions using a unified architecture. The first loop handles frequency acquisition while the second loop handles phase adjustment, and both loops share common circuitry. This multi-functional design achieves high-speed operation without requiring separate dedicated circuits for each function, thereby minimizing silicon area.
4Reliability
If pattern-adaptable error signal selection is implemented to maintain frequency lock, then reliability is improved, but device complexity increases
Solution Approach 1:
The system dynamically selects error signal generation modes based on detected data patterns. The first error block generates error signals for frequency acquisition when specific patterns are detected, while the second error block generates error signals for phase adjustment for other patterns. This dynamic adaptation ensures reliable frequency lock without requiring complex static circuitry for all possible patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves quick frequency lock acquisition and reduced power consumption, maintaining stability with patterns like 1010, and minimizing inter-symbol interference-induced jitter, while optimizing power, area, and design complexity.
Implementation Method 1
a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator
Implementation Method 2
a loop filter configured to control a frequency of the voltage-controlled oscillator based on output of the first error block
Implementation Method 3
a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block
Data Source
AI summary
A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.