Dual-Loop Clock Synchronization Circuit for Multimedia Timing
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Solution Overview
Problem
Communication systems that transmit multimedia content face timing synchronization issues between the source and receiver circuitry due to phase shifts caused by channel dynamics, leading to frame drops, which can be noticeable to users.
Innovation Solution
The implementation of a clock synchronization circuitry using time stamp flags transmitted from the source clock to the receiver, processed through a dual loop digital phase lock loop (DPLL) with numerically controlled oscillators (NCOs) to generate coarse and fine timing signals, ensuring synchronization of the 27 MHz clock and reducing frame drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the receiver uses a local 27 MHz clock that is not synchronized with the source clock, then the receiver can operate independently, but phase shifts accumulate causing timing errors and frame drops
Solution Approach 1:
The patent implements a phase-locked loop (PLL) that continuously monitors the timing relationship between the source and receiver clocks using time-stamp flags, and automatically adjusts the receiver's local clock frequency and phase to match the source clock, eliminating accumulated phase shifts while maintaining independent operation
Solution Approach 2:
The patent introduces time-stamp flags as an intermediary signal that carries timing information from the source to the receiver, enabling the receiver to synchronize its local clock to the source clock without directly connecting the clock signals, thus maintaining operational independence while achieving synchronization
2Measurement precision
If the receiver synchronizes the local clock to the source clock, then timing accuracy is improved, but the system complexity increases due to additional synchronization circuitry
Solution Approach 1:
The patent implements a self-correcting synchronization system where the phase-locked loop automatically detects timing errors through time-stamp flags and self-adjusts the local clock parameters without external intervention, achieving high timing accuracy while keeping the control logic integrated and relatively simple
Data Source
AI summary
A dual loop, clock synchronization circuit for a receiver in a communication system. The circuitry uses a first loop of a digital phase lock loop for coarse synchronization to time stamps within the received data and uses a second loop for fine synchronization of a second numerically controlled oscillator.