Dual-Loop Current-to-Digital Converter for Wide Dynamic Range

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Solution Overview

Problem

Conventional current-to-digital converters face challenges in achieving a wide dynamic range with low power consumption and complexity, particularly in wearable biosensors, due to the limitations of existing structures like prediction DAC, current-splitting DAC, and threshold-filter loop, which are difficult to integrate into small-sized systems and have high power consumption or band limitations.

Innovation Solution

A current-to-digital converter design incorporating a secondary delta-sigma ADC and a truncation-noise-shaped baseline-servo (TNS-BS) loop, utilizing a tri-level RDAC and body-driven VCO quantizer, to efficiently expand the dynamic range while minimizing power consumption and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a prediction DAC structure is used to expand dynamic range, then dynamic range is improved, but device complexity and power consumption increase significantly

Engineering Contradiction:

Improvedynamic rangeVSAvoidcomplexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the dynamic range extension function into two separate loops: a first delta-sigma loop for primary noise shaping and a second baseline-servo loop for truncation noise shaping. This segmentation allows each loop to focus on specific noise components, achieving high dynamic range without requiring complex digital processing blocks that would increase overall device complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces complex digital blocks (typically implemented in FPGA for dynamic range extension) with an integrated analog circuit implementation using dual-loop feedback mechanisms. This substitution enables on-chip integration while maintaining high dynamic range performance, reducing both device complexity and power consumption compared to external FPGA implementations.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If digital blocks are used to expand dynamic range in hourglass ADC, then dynamic range is improved, but power consumption increases and integration becomes difficult

Engineering Contradiction:

Improvedynamic rangeVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent merges the dynamic range extension function directly into the ADC circuit by integrating the two-loop feedback structure (delta-sigma loop and baseline-servo loop) within the analog domain. This consolidation eliminates the need for separate external digital processing blocks, reducing power consumption and enabling full on-chip integration while achieving 120 dB or higher dynamic range.

Inventive Principle:

Principle #5Merging (Combining)

3Area of stationary object

If a single current-to-digital converter is used to measure multiple analytes, then device size is reduced, but achieving wide dynamic range becomes more challenging

Engineering Contradiction:

Improvedevice areaVSAvoiddynamic range

Core Design Contradiction:

Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent designs a universal current-to-digital converter with a dual-loop architecture that can accurately measure multiple analytes across a wide dynamic range (120 dB or more). The first delta-sigma loop handles primary conversion while the second baseline-servo loop extends the dynamic range, allowing a single converter to replace multiple specialized converters, thereby reducing device area while maintaining high measurement precision for various analyte concentrations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Ease of manufacture

If conventional ADC structures are used, then integration is easier, but dynamic range is limited and power consumption is high

Engineering Contradiction:

Improveintegration easeVSAvoiddynamic range

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent implements a dynamic dual-loop feedback architecture where the first delta-sigma loop and second baseline-servo loop work together adaptively. The loops dynamically adjust their operation to handle different input signal levels, enabling the converter to achieve high dynamic range (120 dB or more) while maintaining ease of CMOS integration and low power consumption, outperforming conventional static ADC structures.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12463656B2Current-to-digital converter with wide dynamic range

Publication Date: 2025.11.04 DAEGU GYEONGBUK INSTITUTE OF SCIENCE AND TECHNOLOGY

AI summary

The present invention relates to a current-to-digital converter and the current-to-digital converter according to an example embodiment includes an integrator connected to a current source that outputs input current; a quantizer connected to the integrator and configured to generate a first digital output code corresponding to alternating current (AC) in the input current; a first loop circuit formed on a delta-sigma (ΔΣ) loop that connects an input terminal of the integrator and an output terminal of the quantizer; a second loop circuit formed on a truncation-noise-shaped baseline-servo (TNS-BS) loop that connects the input terminal of the integrator and the output terminal of the quantizer and configured to generate a second digital output code corresponding to direct current (DC) in the input current; and an adder configured to generate a final digital output code by adding the first digital output code and the second digital output code.