Dual-Loop DLL Clock Alignment for Multi-Domain Serializer Timing
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Solution Overview
Problem
High-frequency serializers with wide bit-width, such as digital-to-analog converters (DACs) and direct digital frequency synthesizers (DDS), face challenges in synchronizing multiple clock domains due to variations in temperature, semiconductor process, and voltage, leading to phase alignment issues that can result in setup and hold violations and increased bit-error rates.
Innovation Solution
A dual-loop (coarse and fine) delay-locked loop (DLL) system with glitch-less coarse switching and an unlimited phase acquisition range is employed to synchronize clock domains, using a coarse DLL to generate evenly spaced phases and a fine DLL to force phase alignment, maintaining synchronization across temperature, voltage, and process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock domain is used to drive both high-frequency serializer and lower-frequency data circuits, then device complexity is reduced, but phase alignment between clock domains cannot be maintained under temperature, voltage, and process variations
Solution Approach 1:
The patent divides the clock alignment function into two separate clock domains: a first clock domain for the high-frequency serializer and a second clock domain for the lower-frequency data circuits. Each domain operates independently with its own clock signal, allowing them to be optimized and stabilized separately rather than forcing a single clock to serve both functions, which would compromise phase alignment under variations.
Solution Approach 2:
The patent introduces a dual-loop delay-locked loop (DLL) system as an intermediary mechanism between the two clock domains. The DLL includes a coarse loop that generates multiple phase-shifted clock signals and a fine loop that selects and adjusts the appropriate phase to align the second clock domain with the first. This intermediary structure enables precise phase alignment while maintaining the independence and stability of both clock domains under temperature, voltage, and process variations.
2Adaptability or versatility
If a coarse DLL with multiple phase-shifted clock signals is used to cover large phase differences, then phase acquisition range is improved, but switching between phases may cause clock glitches
Solution Approach 1:
The patent implements a dynamic phase selection mechanism in the fine DLL that continuously monitors phase alignment and adjusts the selected phase from the coarse DLL in real-time. This dynamic adjustment allows the system to adapt to varying phase differences while maintaining smooth transitions between phases, preventing clock glitches that would occur with static or abrupt switching.
Solution Approach 2:
The patent employs a feedback mechanism where the phase alignment between the two clock domains is continuously monitored and fed back to the dual-loop DLL system. The coarse loop uses feedback to determine the appropriate phase shift, and the fine loop uses feedback to make precise adjustments. This closed-loop feedback ensures that phase transitions are smooth and controlled, eliminating clock glitches while maintaining unlimited phase acquisition range.
3Manufacturing precision
If a fine DLL with limited phase adjustment range is used to achieve precise phase alignment, then manufacturing precision is improved, but the system cannot maintain alignment across all possible phase differences
Solution Approach 1:
The patent segments the phase adjustment function into two parts: a coarse adjustment stage that handles large phase differences by selecting from multiple phase-shifted clock signals, and a fine adjustment stage that handles precise alignment within a limited range. This segmentation allows each stage to be optimized for its specific function - the coarse stage provides unlimited range while the fine stage provides high precision, and together they achieve both goals simultaneously.
Data Source
AI summary
A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.