Dual-Loop DLL Circuit for Multi-Phase Clock Synchronization
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Solution Overview
Problem
Existing DLL circuits struggle to synchronize internal and external clock signals in semiconductor memory devices, especially when memory cells are activated, leading to changes in supply voltage that affect clock signal synchronization, and they are not configured to handle multi-phase clock signals effectively.
Innovation Solution
A dual-loop DLL circuit is introduced, comprising a basic loop and a coarse loop, which generates multiple clock signals with varying phases, a delay model, and a fine loop to synchronize clock signals, using phase detectors, charge pumps, loop filters, and multi-phase voltage-controlled delay lines to adjust delay times and phase differences, allowing for synchronization of internal and external clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-loop DLL circuit is used, then the circuit complexity is low, but it cannot effectively synchronize multi-phase clock signals when supply voltage changes
Solution Approach 1:
The DLL circuit is divided into two independent loops: a coarse loop that handles large phase adjustments and a fine loop that handles precise phase adjustments. Each loop has its own phase detector, charge pump, and delay line, allowing them to operate independently and be optimized for their specific functions.
Solution Approach 2:
The system dynamically switches between coarse and fine loops based on operating conditions. When supply voltage changes occur, the coarse loop performs initial synchronization, and then the fine loop takes over for precise phase matching, enabling adaptive response to different voltage conditions.
2Reliability
If the DLL circuit performs shift operations to compensate for voltage changes, then clock signal synchronization is maintained, but phase errors and jitter noise increase
Solution Approach 1:
The fine loop provides continuous dynamic adjustment of phase by controlling the delay amount of the fine delay line based on phase detection results, eliminating the need for discrete shift operations and thereby reducing phase errors and jitter.
3Adaptability or versatility
If multi-phase clock signals are generated, then the functionality for memory operations is improved, but the circuit complexity and power consumption increase
Solution Approach 1:
Both the coarse and fine delay lines are designed to generate multiple phased clock signals simultaneously. The same delay line structure and control mechanism are used across different phases, allowing a single circuit design to serve multiple phase generation needs without proportionally increasing complexity.
4Measurement precision
If the fine loop is always activated for precise delay adjustments, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The system dynamically activates only the fine loop when precise phase adjustment is needed, such as when supply voltage changes occur and the coarse loop has completed initial synchronization. This dynamic activation strategy maintains high synchronization accuracy while minimizing power consumption during normal operation.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a basic loop, a coarse loop, a delay model and a fine loop. The basic loop generates a plurality of first clock signals, based at least in part on an input clock signal, a feedback clock signal and a fine loop output signal. The first clock signals respectively have a phase difference. The coarse loop generates a plurality of output clock signals, based at least in part on the input clock signal, the feedback clock signal and the first clock signals. The plurality of output clock signals respectively have a phase difference. The delay model generates the feedback clock signal by delaying one of the output clock signals by a first time period. The fine loop generates the fine loop output signal, based at least in part on the input clock signal and the feedback clock signal.