Dual-Loop Delay-Locked Circuit for Stable Phase Adjustment

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Solution Overview

Problem

Delay-locked loops (DLLs) in integrated circuits face challenges in quickly and effectively adjusting to voltage, temperature, and process variations, leading to inadequate phase-lock of output clock signals due to single feedback control systems.

Innovation Solution

Implementing a dual feedback loop system within the DLL, where the first feedback loop generates a feedback signal for phase difference adjustments and the second feedback loop generates a regulated signal to control a resistor-capacitor network, enabling both loops to compensate for voltage and temperature variations across different frequency ranges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single feedback control system is used in a delay-locked loop, then the device complexity is reduced, but the responsiveness to voltage, temperature, and process variations is insufficient

Engineering Contradiction:
Improvephase-locking performanceVSAvoidfeedback control system structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The single feedback control system is segmented into two independent feedback loops: a first feedback loop for rapid response to high-frequency variations and a second feedback loop for comprehensive compensation of low-frequency variations. This segmentation allows each loop to be optimized for specific frequency ranges, improving overall reliability without requiring a completely complex new system architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a frequency dimension to the feedback control by designing the first feedback loop with higher bandwidth for high-frequency responses and the second feedback loop with lower bandwidth for low-frequency responses. This dimensional differentiation in frequency response characteristics enables the system to handle multiple types of variations simultaneously, resolving the contradiction between simplicity and responsiveness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the feedback loop increases the delay range to cover variations, then the adaptability improves, but the response speed to variations decreases

Engineering Contradiction:
Improvecompensation range for variationsVSAvoidresponse speed to variations
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The compensation function is segmented between two feedback loops with different characteristics. The first feedback loop provides rapid response for small-signal, high-frequency variations with shorter delay adjustments, while the second feedback loop provides broader compensation for large-signal, low-frequency variations with larger delay adjustments. This segmentation resolves the contradiction by assigning different response-speed and range-requirements to different segments of the control system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each feedback loop is designed with local quality optimized for its specific operating range. The first feedback loop has high bandwidth and low delay range optimized for rapid responses, while the second feedback loop has lower bandwidth and high delay range optimized for comprehensive compensation. This local optimization allows the system to achieve both speed and adaptability in their respective domains.

Inventive Principle:
Principle #3Local quality

3Stability of the object's composition

If filtering is increased to reduce noise, then the stability improves, but the response to variations becomes slower

Engineering Contradiction:
Improvesignal stabilityVSAvoidresponse speed
Core Design Contradiction:
Stability of the object's compositionVSSpeed

Solution Approach 1:

The filtering function is segmented between two feedback loops. The first feedback loop uses minimal filtering to maintain high bandwidth and fast response speed for high-frequency variations. The second feedback loop uses stronger filtering to achieve stability and noise reduction for low-frequency variations. This segmentation allows the system to maintain both speed and stability by applying appropriate filtering only where needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent addresses the speed-stability contradiction by introducing a frequency dimension to filtering. Different filtering strengths are applied at different frequency ranges: light filtering for high frequencies to preserve response speed, and heavy filtering for low frequencies to ensure stability. This frequency-dependent filtering strategy resolves the contradiction between response speed and signal stability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This dual feedback loop system enhances the DLL's responsiveness to variations, providing a wider frequency and delay range, making it more robust to both low-frequency and high-frequency changes, thus improving the phase-locking performance.

Implementation Method 1

The chain of delay elements forms a resistor-capacitor network in the variable delay circuit. The feedback signal generated in the first feedback loop controls a capacitance of the resistor-capacitor network, and the regulated signal controls a resistance of the resistor-capacitor network.

Methodology Applied
Scientific EffectRC time constant: Capacitance

Data Source

PatentUS8704570B2Delay-locked loop with phase adjustment
Publication Date: 2014.04.22 MOSYS INC
  • US8704570B2 patent drawing
  • US8704570B2 patent drawing
  • US8704570B2 patent drawing

AI summary

A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.