Dual Loop Adaptive LDO Voltage Regulator Circuit
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Solution Overview
Problem
Conventional voltage regulator circuits often require external capacitors, limiting the distribution of multiple instances on an integrated circuit and necessitating specific tuning for different load circuits, which affects stability and responsiveness.
Innovation Solution
A low drop-out (LDO) voltage regulator circuit incorporating a voltage loop and a current loop, where the current loop quickly adjusts load current and the voltage loop fine-tunes output voltage, eliminating the need for external capacitors and enabling load-adaptive operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If external capacitors are used to stabilize voltage regulator output, then stability is improved, but device complexity and area increase, and multiple instances cannot be distributed on integrated circuit
Solution Approach 1:
The patent extracts the capacitor function from external components and implements it internally using a current mirror circuit. The current mirror stabilizes the output voltage by replicating the reference current through multiple transistors, eliminating the need for external capacitors while maintaining voltage stability.
Solution Approach 2:
The patent merges the voltage regulation function and current stabilization function into a single integrated circuit block. The voltage regulator stage combines the amplifier, PMOS transistor, and current mirror in one unit, allowing multiple instances to be distributed on the integrated circuit without requiring external capacitors.
2Stability of the object's composition
If conventional voltage regulator circuits are designed for stability with external capacitors, then stability is improved, but responsiveness to load variations deteriorates
Solution Approach 1:
The patent implements a dynamic response system where the amplifier continuously adjusts the gate voltage of the PMOS transistor based on feedback from the output voltage. This dynamic feedback mechanism allows the circuit to quickly respond to load variations while maintaining stability, eliminating the trade-off between stability and responsiveness.
Solution Approach 2:
The patent employs a feedback loop where the output voltage is monitored and fed back to the amplifier, which adjusts the control voltage on the PMOS transistor gate. This closed-loop feedback system ensures both stability and fast response to load changes by continuously correcting deviations from the desired output voltage.
3Device complexity
If voltage regulator stages are implemented on integrated circuit without external capacitor connections, then device complexity is reduced and distribution is enabled, but stability deteriorates
Solution Approach 1:
The patent implements a self-stabilizing voltage regulator where the current mirror circuit automatically stabilizes the output voltage without requiring external capacitors. The current mirror uses the inherent properties of matched transistors to replicate the reference current, creating a self-regulating system that maintains stability internally.
Solution Approach 2:
The patent creates a universal voltage regulator block that can be distributed multiple times on the integrated circuit without requiring external components. The current mirror design provides both voltage regulation and current stabilization functions in a single integrated block, making it universally applicable across multiple instances.
Data Source
AI summary
A voltage regulator circuit is disclosed. In one embodiment, a low drop-out (LDO) voltage regulator includes a voltage loop and a current loop. The current loop includes a source follower coupled to an output node of the LDO voltage regulator, the source follower being implemented with a PMOS transistor. The current loop also includes a current mirror coupled between a first branch of the current loop and a second branch of the current loop. The source follower is implemented in the second branch of the current loop. The voltage loop includes an amplifier circuit having an inverting input coupled to the output node, and a non-inverting input coupled to receive a reference voltage. The output of the amplifier is coupled to the gate terminal of the PMOS transistor of the current mirror.