Dual-Loop Level Shifter for Controlled Output Latching
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Solution Overview
Problem
Current level shifter designs lack controllable output latching, leading to malfunctions and unpredictable situations during core re-power-up sequences, and suffer from larger silicon area, increased power consumption, complexity, and duty cycle distortion.
Innovation Solution
A dual loop level shifter is introduced, comprising a PMOS/NMOS cross latch loop and an inverter cross latch loop, where the state of the first latch loop is maintained by the second loop using transmission gates, enabling controlled output latching and minimizing duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single loop level shifter is used, then the device complexity is reduced, but the controllable output latching feature is lost leading to malfunctions during core re-power-up sequences
Solution Approach 1:
The level shifter is divided into two functional segments: a first latch loop (PMOS/NMOS cross latch) for normal level translation and a second latch loop (inverter cross latch) for controlled output latching. This segmentation allows each loop to perform its specific function independently, achieving reliable output latching control while maintaining manageable device complexity through modular architecture.
2Reliability
If known single loop level shifters with controllable output latching are used, then the output latching feature is achieved, but silicon area increases
Solution Approach 1:
The patent merges the level translation function and the output latching function into a single integrated dual-loop structure where the first and second latch loops share common transistors and nodes. This merging eliminates the need for separate independent latch circuits, achieving reliable output latching control while minimizing silicon area through resource sharing.
3Reliability
If known single loop level shifters with controllable output latching are used, then the output latching feature is achieved, but power consumption increases
Solution Approach 1:
The level shifter dynamically switches between two operational modes: normal level translation mode using the first latch loop and output latching mode using the second latch loop. The control signal dynamically enables or disables specific transistors to activate the appropriate loop, achieving reliable output latching control while minimizing power consumption by only activating the necessary circuitry for each operational state.
4Reliability
If known single loop level shifters with controllable output latching are used, then the output latching feature is achieved, but duty cycle distortion increases
Solution Approach 1:
The patent introduces transmission gates as intermediary elements that precisely control the coupling between the first and second latch loops. These transmission gates act as mediators that enable clean state transfer from the first loop to the second loop during latching operations, achieving reliable output latching control while minimizing duty cycle distortion through precise timing and isolation of the two loops.
Data Source
AI summary
A method and apparatus are disclosed to control one or more input output (I/O) pads. An input signal is translated to an output signal having a desired logic level using a first latch loop. The state of the first latch loop is maintained by a second latch loop, integrated with the first latch loop, when a latching indication is received. The integration between the first latch loop and the second latch loop is such that the second latch loop creates an input-output connection if transmission gates in the second latch loop are conductive, and disables the input-output connection if the transmission gates are not conductive.