Switchable Dual-Loop PLL for Low Jitter and Wide Lock Range
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing PLL circuits face challenges in achieving low jitter while maintaining a large locking range, as TCXOs provide excellent stability but limited locking range, and VCXOs offer larger locking range but higher jitter.
Innovation Solution
Combining two PLL circuits with one using a TCXO for stability and the other a VCXO for range, with a lock detector switching between configurations to optimize jitter and locking performance based on input signal presence and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a TCXO is used in a PLL circuit, then frequency and phase stability is improved, but the locking range becomes very small
Solution Approach 1:
The PLL circuit is divided into two separate PLL circuits (first PLL and second PLL), each with different oscillator types. The first PLL uses a TCXO for stability while the second PLL uses a VCXO for larger locking range. This segmentation allows each segment to specialize in one aspect, resolving the contradiction between stability and adaptability.
Solution Approach 2:
The circuit dynamically switches between different configurations based on operating conditions. A lock detector monitors the locking status and controls switches to change the circuit configuration. This dynamic adaptation allows the system to optimize between stability and locking range based on real-time conditions.
2Adaptability or versatility
If a VCXO is used in a PLL circuit, then the locking range becomes larger, but the output signal exhibits higher clock jitter
Solution Approach 1:
The circuit segments the locking function across two PLL circuits with different oscillator characteristics. The VCXO-based second PLL provides the larger locking range while the TCXO-based first PLL provides the stable reference with low jitter. This segmentation allows the system to achieve both large locking range and low jitter simultaneously.
Solution Approach 2:
The first PLL circuit acts as an intermediary between the input signal and the second PLL circuit. It receives the input signal, stabilizes it with its TCXO, and provides a low-jitter reference to the second PLL, thereby mediating the trade-off between locking range and jitter.
3Device complexity
If only one PLL circuit is used, then the device complexity is reduced, but it cannot simultaneously provide large locking range and low jitter
Solution Approach 1:
The invention merges two PLL circuits with complementary characteristics into a single integrated system. By combining the TCXO-based first PLL and the VCXO-based second PLL with switching control, the system achieves performance capabilities that neither circuit could provide alone, while maintaining a unified circuit architecture.
Solution Approach 2:
The circuit employs dynamic switching between different operational modes controlled by a lock detector. This dynamic control allows the system to adapt its complexity and configuration based on operating conditions, providing both large locking range and low jitter performance without requiring permanently complex circuitry in all operating states.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An electronic circuit includes a first and a second PLL stage (PLL1, PLL2) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL2) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL1) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL1) to the input signal (IN) and, upon locking, sets switches (S1, S2) to couple the output of the first PLL circuit (PLL1) to the input of the second PLL circuit (PLL2), and to couple the output of the second PLL circuit (PLL2) to the input of the first PLL circuit (PLL1).