Dual-Loop PLL Architecture for Wide-Range RF Frequency Locking
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Solution Overview
Problem
Conventional RF receivers face challenges with external components in PLL circuits, leading to increased costs and power consumption due to the use of capacitor-based integrators and operational amplifiers, as well as time and power-consuming two-stage search and lock strategies that require recalibration, disrupting signal processing.
Innovation Solution
A dual-loop phase lock loop (PLL) with coarse and fine tuning circuitry arranged in parallel, providing tuning signals to a voltage-controlled oscillator, enabling a highly integratable solution with a wide frequency lock range and low phase noise, eliminating the need for external components and reducing recalibration requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional PLL circuits use capacitor-based integrators and operational amplifiers, then the PLL can achieve frequency locking, but external components are required which increases device complexity and reduces integrability
Solution Approach 1:
The patent merges the capacitor-based integrator and operational amplifier functions into a single integrated circuit block, eliminating the need for external capacitors and resistors. This consolidation achieves full integration of the PLL circuit while maintaining the frequency locking capability through on-chip implementation of all necessary components.
2Reliability
If conventional PLLs use two-stage search and lock strategies, then frequency locking can be achieved, but recalibration is required which consumes time and power
Solution Approach 1:
The patent implements a dual-loop architecture where a coarse tuning loop performs preliminary frequency acquisition and a fine tuning loop subsequently achieves precise frequency locking. This preliminary action in the coarse loop eliminates the need for recalibration by ensuring the VCO is already within the capture range of the fine tuning loop before signal processing begins.
3Measurement precision
If conventional PLLs undergo recalibration during operation, then frequency accuracy can be maintained, but signal processing time is lost
Solution Approach 1:
The patent maintains continuous frequency locking through the dual-loop architecture where both coarse and fine tuning loops operate simultaneously and continuously. The coarse loop continuously tracks gross frequency deviations while the fine loop maintains precise locking, eliminating interruptions for recalibration and ensuring uninterrupted signal processing.
4Reliability
If conventional PLL circuits use external capacitors and resistors, then the circuit can function, but power consumption increases
Solution Approach 1:
The patent combines all passive components (capacitors and resistors) and active components (operational amplifiers) into a single integrated circuit implementation. This merging eliminates the need for external components and reduces overall power consumption by minimizing the number of discrete components and their associated power requirements while maintaining full circuit functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-loop PLL solution enhances integration, reduces phase noise, and minimizes recalibration needs, resulting in improved performance and efficiency by allowing the RF receiver to lock onto desired frequencies with high sensitivity and reduced power consumption.
Implementation Method 1
Both of the coarse tuning circuitry and fine tuning circuitry provide respective tuning signals to a voltage-controlled oscillator (VCO)
Implementation Method 2
a varactor-tuned VCO
Data Source
AI summary
A method and apparatus for providing a dual-loop phase lock loop (PLL) for a radio-frequency (RF) receiver is provided. The dual-loop PLL may include coarse tuning circuitry and fine tuning circuitry. The coarse turning circuitry and fine tuning circuitry may be arranged in parallel. Both of the coarse tuning circuitry and fine tuning circuitry provide respective tuning signals to a voltage-controlled oscillator (e.g., a varactor tuned VCO). The coarse tuning circuitry and the fine tuning circuitry may provide the respective tuning signals simultaneously. In addition, coarse and fine tuning circuitry may be formed monolithically with other elements of the dual-loop PLL so as to provide a highly-integratable having a wide frequency lock range and high sensitivity.