Dual-Loop PLL Synthesizer for Low Phase Noise and Spur Suppression
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Solution Overview
Problem
Existing synthesizers face limitations in suppressing fractional spurious components and phase noise deterioration when finer frequency settings are made, restricting resolution and degrading phase noise characteristics.
Innovation Solution
A parallel-type double loop configuration is implemented, combining a fine-adjustment synthesizer using an integer-type PLL for arbitrary frequency generation and a coarse-adjustment synthesizer with low phase noise characteristics, both operating on a reference signal source with low phase noise, and utilizing power addition through a mixer to reduce phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional PLL is used to generate arbitrary frequency with fine resolution, then frequency resolution is improved, but fractional spurious components occur in the vicinity of oscillation frequency
Solution Approach 1:
The invention divides the frequency synthesis function into two separate integer PLL loops: a first loop for generating a high frequency signal and a second loop for generating a reference signal. This segmentation allows each loop to operate as an integer PLL, avoiding fractional spurious components while achieving fine frequency resolution through the interaction of the two loops.
Solution Approach 2:
The second loop acts as an intermediary that adjusts the reference frequency of the first loop to a target frequency. By using the output of the second loop as the reference for the first loop, the system achieves fine frequency resolution without requiring fractional division, thus eliminating fractional spurious components.
2Object-generated harmful factors
If a double feedback loop is used to suppress spurious components, then spurious component suppression is improved, but phase noise deteriorates due to voltage addition of two synthesizers
Solution Approach 1:
Both the first loop and second loop use integer PLL configurations with matching reference frequencies, ensuring homogeneous phase noise characteristics. This homogeneity prevents the phase noise deterioration that would occur with voltage addition of heterogeneous synthesizer outputs.
Solution Approach 2:
The second loop essentially creates a copied and adjusted version of the reference signal for the first loop. By copying the reference frequency generation mechanism and applying it to adjust the first loop's reference, the system maintains consistent phase noise characteristics while achieving spurious component suppression.
Data Source
AI summary
A fine-adjustment synthesizer includes a fractional phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a frequency variable oscillator, a mixer, a baud-pass filter, and a feedback path programmable fractional frequency divider. A coarse-adjustment synthesizer includes an integer-type phase-locked loop having a reference integer frequency divider, a phase comparator, a loop filter, a frequency variable oscillator, a band-pass filter, and a feedback path programmable integer frequency divider. An output of a reference signal source is input in parallel to both the fine-adjustment synthesizer and the coarse-adjustment synthesizer. An output of the frequency variable oscillator in the fine-adjustment synthesizer and an output of the frequency variable oscillator in the coarse-adjustment synthesizer are guided to the mixer and an output signal of the fine-adjustment synthesizer is guided to an output end.