Dual-Loop Regulator Circuit for High-PSRR Noise Rejection
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Solution Overview
Problem
Existing low-dropout voltage regulators (LDOs) face challenges in effectively rejecting power supply noise and voltage ripple, particularly in applications requiring high power supply rejection ratio (PSRR) for stable output voltage in audio circuits and analog-to-digital converters.
Innovation Solution
The regulator circuit incorporates a slow loop circuit and a fast loop circuit, with the slow loop using a transistor and amplifier to adjust output voltage based on a reference voltage, and the fast loop using parallel power circuits to quickly respond to voltage changes, reducing high-frequency noise and improving PSRR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-loop voltage regulator circuit is used, then the circuit structure is simple, but the power supply rejection ratio (PSRR) is insufficient and high-frequency noise cannot be effectively rejected
Solution Approach 1:
The voltage regulator circuit is divided into two independent loops: a slow loop for low-frequency noise rejection and a fast loop for high-frequency noise rejection. Each loop has its own error amplifier and feedback path, allowing them to operate independently and address different frequency ranges without interfering with each other
Solution Approach 2:
The patent extends the single-loop design into a two-dimensional frequency domain by creating separate control paths for different frequency ranges. The slow loop handles low-frequency variations while the fast loop handles high-frequency noise, effectively adding a frequency dimension to the control architecture
2Speed
If the feedback node is directly connected to the gate of the power transistor, then the response speed is fast, but noise is easily introduced and stability deteriorates
Solution Approach 1:
The feedback path is segmented into two separate paths: one for the slow loop and one for the fast loop. Each path has its own error amplifier and feedback network, allowing the system to achieve fast response through the fast loop while maintaining stability through the slower, more stable slow loop path
Solution Approach 2:
The patent introduces intermediate error amplifiers in both loops that act as mediators between the feedback node and the power transistor gate. These amplifiers filter and condition the feedback signal, preventing direct coupling of high-frequency noise while maintaining the ability to respond quickly to voltage changes
Data Source
AI summary
A regulator circuit includes a slow loop circuit and a fast loop circuit. The slow loop circuit includes an amplifier and a first transistor coupled between an output terminal and a first node. The first transistor adjusts a first voltage of the output terminal. The first voltage is configured as a regulated power source voltage. The fast loop includes multiple power circuits coupled in parallel between the output terminal and the first node. Each of the power circuits includes a power transistor coupled between a supply voltage and the output terminal. The power circuit adjusts a conductivity of the power transistor according to a second voltage of the first node to adjust the first voltage of the output terminal.