Dual-Loop SAR ADC Architecture for Speed and Meta-Stability
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Solution Overview
Problem
In deep sub-micron FinFET process technologies, achieving high-speed analog-to-digital converters (ADCs) is challenging due to conflicting requirements between asynchronous and synchronous SAR architectures, which prevent simultaneous high speed and low comparator meta-stability.
Innovation Solution
A mixed synchronous/asynchronous SAR-based ADC architecture is introduced, where the asynchronous portion is layout-driven based on process constraints, and the synchronous portion is circuit-driven independently, allowing for the separation of limitations and extraction of benefits from each architecture without performance compromises.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous SAR architecture is used, then comparator meta-stability is minimized, but conversion speed is limited to moderate levels
Solution Approach 1:
The ADC is divided into two independent loops: an asynchronous inner loop for bit determination (avoiding meta-stability) and a synchronous outer loop for timing control (achieving high speed). Each loop operates independently with its own comparators and control logic, allowing optimization of each for its specific function.
Solution Approach 2:
The patent implements dynamic switching between asynchronous and synchronous operation modes. The outer synchronous loop dynamically controls the timing and enables the inner asynchronous loop to operate only when needed for comparison, combining the speed benefits of synchronous operation with the reliability of asynchronous comparison.
2Speed
If synchronous SAR architecture is used, then conversion speed is increased, but comparator meta-stability risk increases
Solution Approach 1:
The ADC is divided into two independent loops: an asynchronous inner loop for bit determination (avoiding meta-stability) and a synchronous outer loop for timing control (achieving high speed). Each loop operates independently with its own comparators and control logic, allowing optimization of each for its specific function.
Solution Approach 2:
The patent implements dynamic switching between asynchronous and synchronous operation modes. The outer synchronous loop dynamically controls the timing and enables the inner asynchronous loop to operate only when needed for comparison, combining the speed benefits of synchronous operation with the reliability of asynchronous comparison.
3Speed
If deep sub-micron FinFET process is used, then device speed is increased, but layout parasitics and geometric constraints limit achievable circuit speed
Solution Approach 1:
The design separates layout-critical components (comparators in inner loop) from timing-critical components (outer loop control). The inner loop can be optimized for layout matching and parasitic minimization, while the outer loop handles high-speed timing independently, allowing each to be optimized for its specific requirements.
Solution Approach 2:
The state machine acts as an intermediary between the asynchronous comparison results and the synchronous output timing. It buffers and conditions the signals, isolating the sensitive comparator outputs from the high-speed synchronous timing requirements, thereby reducing the impact of layout parasitics on overall performance.
Data Source
AI summary
A dual-loop analog to digital converter (ADC) includes an asynchronous inner loop including first and second comparators and a state machine, where outputs of the first and second comparators are coupled to inputs of the state machine, and where outputs of the state machine are cross-coupled to enable ports of the first and second comparators. The ADC includes a synchronous outer loop including a successive approximation register (SAR), a digital to analog converter (DAC), and the first and second comparators, where the outputs of the first and second comparators are coupled to inputs of the SAR, an N-bit output of the SAR is coupled to an N-bit input of the DAC, and a differential output of the DAC is coupled to inputs of the first and second comparators, where a state of the state machine is independent of the state of the SAR.