Dual-Loop Passive Sigma-Delta Modulator With Error-Canceling Second Loop

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional sigma-delta converters face limitations in reducing size and power consumption while maintaining performance, as they become more sensitive to noise and metastability due to reduced signal strength, and existing solutions like MASH structures increase size and power consumption with complex calibration requirements.

Innovation Solution

A dual loop passive sigma-delta modulator is implemented, using passive components for summing junctions and integrators, with a second loop to convert and cancel quantization errors, reducing noise and power consumption by minimizing active circuitry and employing noise cancellation filters to enhance signal-to-noise ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If passive components are used for summing junctions and integrators to reduce power consumption, then power consumption is reduced, but the modulator becomes more sensitive to comparator input noise and metastability

Engineering Contradiction:
Improvepower consumptionVSAvoidsensitivity to noise and metastability
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

The single-loop passive modulator is segmented into two cascaded loops: a first passive modulator loop and a second passive modulator loop. This segmentation allows the system to maintain passive component benefits while improving noise immunity through the combined operation of both loops, effectively resolving the contradiction between low power consumption and noise sensitivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second passive modulator loop provides feedback to cancel quantization errors from the first loop. This feedback mechanism improves the overall signal-to-noise ratio and reduces sensitivity to comparator input noise and metastability, while both loops continue to use passive components to maintain low power consumption.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If MASH structure is used to increase performance, then quantization error is converted, but size and power consumption increase significantly

Engineering Contradiction:
Improvequantization error conversionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The invention replaces active circuitry (mechanical/electronic amplification systems) with passive circuitry (RC networks, capacitors, and switches) to implement the MASH structure. This substitution maintains the quantization error conversion capability while dramatically reducing power consumption and circuit size by eliminating the need for high-gain active amplifiers.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If MASH structure is used to increase performance, then quantization error is converted, but device complexity increases with compensation filter calibration

Engineering Contradiction:
Improvequantization error conversionVSAvoidcompensation filter calibration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The dual-loop passive modulator structure is designed to automatically cancel quantization errors through the inherent operation of the two cascaded passive loops. The system is self-calibrating and does not require external compensation filters or trial-and-error calibration procedures, thereby reducing device complexity while maintaining high measurement precision.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11502698B1Dual loop passive sigma-delta modulator
Publication Date: 2022.11.15 NXP BV
  • US11502698B1 patent drawing
  • US11502698B1 patent drawing
  • US11502698B1 patent drawing

AI summary

A passive sigma-delta modulator including first modulator loop, a second modulator loop, and a digital combiner providing an output signal. The first modulator loop includes a first quantizer, a first passive summing junction, a first continuous-time passive analog loop filter, and a first feedback path. The second modulator loop includes a second quantizer, analog transfer circuitry, a second continuous-time passive summing junction, a second passive analog loop filter, a second feedback path, and digital transfer circuitry having a gain that is substantially a reciprocal of the analog transfer circuitry. A digital noise cancelation filter may be located between the first quantizer and the digital combiner, or an analog noise cancelation filter may be provided within the second modulator loop. Single-ended or differential configurations are contemplated.