Dual-Loop Frequency Synthesizer for Spur-Reduced Wideband Tuning
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Solution Overview
Problem
Fractional-N synthesizers suffer from spurious sideband signals due to carrier frequency crossing harmonics of the phase frequency detector sampling frequency, degrading performance, especially in wide bandwidth applications, and require a solution for adaptable tuning with reduced size, weight, power, and complexity.
Innovation Solution
A dual-loop frequency synthesizer architecture incorporating a fractional loop and an integer loop, with a fractional divider and integer divider respectively, constrained to operate between adjacent harmonics of a reference frequency, to minimize spurious sidebands and provide high-resolution, wide-band frequency signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional-N synthesizer is used to provide adaptable tuning and wide bandwidth, then frequency resolution and tuning range are improved, but spurious sideband signals are generated that degrade performance
Solution Approach 1:
The synthesizer is divided into two separate loops: an integer-N loop and a fractional-Strobe loop. The integer loop handles the main frequency synthesis with high stability, while the fractional loop provides fine frequency adjustments. This segmentation allows the system to achieve adaptable tuning without generating spurious sidebands, as each loop operates independently with its own phase frequency detector and feedback path.
2Adaptability or versatility
If the carrier frequency crosses harmonics of the phase frequency detector sampling frequency, then wide bandwidth coverage is achieved, but integer boundary spurs and fractional spurs are generated
Solution Approach 1:
A dual-modulus prescaler is introduced as an intermediary component between the VCO and the phase frequency detectors. This prescaler can operate in two modes (integer and fractional) and acts as a mediator that prevents the carrier frequency from directly crossing harmonics of the PFD sampling frequency. By using the prescaler as an intermediate stage, the system achieves wide bandwidth coverage while avoiding the generation of integer boundary spurs and fractional spurs.
3Measurement precision
If a traditional fractional-N synthesizer architecture is used, then frequency resolution is improved, but device size, weight, power consumption, and complexity increase
Solution Approach 1:
The integer-N loop and fractional-Strobe loop are merged into a single integrated synthesizer architecture that shares common components such as the VCO, reference oscillator, and power supply. This merging reduces the overall device complexity, size, and power consumption while maintaining high frequency resolution. The shared components eliminate redundancy and simplify the circuit design compared to completely separate integer and fractional synthesizers.
Data Source
AI summary
A frequency synthesizer has a fractional N1 loop and an integer N2 loop. The output frequency of the signal of the fractional N1 loop is constrained to values between adjacent harmonics of a reference frequency used in the fractional N1 loop. The signal of the fractional N1 loop is received by the integer N2 loop. The integer N2 loop provides an output signal. The output signal can be a high frequency signal such as 2-8 GHz signal.