Dual Masking Layers for FinFET Impurity Control
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Solution Overview
Problem
Current methods for manufacturing FinFETs face challenges in precisely controlling impurity implantation and gate electrode formation, leading to potential short circuits and unstable breakdown voltages due to inadequate mask member design and etching processes.
Innovation Solution
A method involving a two-layer silicon nitride mask structure, where a wider upper-side mask and a narrower lower-side mask are used sequentially for impurity implantation and gate electrode formation, respectively, to prevent impurity contamination and ensure precise mask member shapes for each process step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single mask member is used for impurity implantation and gate electrode formation, then the manufacturing process is simpler, but impurity distribution control and mask shape precision deteriorate
Solution Approach 1:
The mask member is divided into two distinct layers: a first mask layer (silicon nitride) and a second mask layer (oxide). The first mask layer controls impurity implantation depth and distribution, while the second mask layer defines the gate electrode shape and width. This segmentation allows each layer to be optimized for its specific function, achieving precise control over both impurity distribution and mask shape that cannot be obtained with a single mask structure.
2Reliability
If mask thickness is increased to prevent short circuits, then device reliability improves, but manufacturing complexity increases
Solution Approach 1:
Instead of using a single thick mask layer, the patent segments the mask into two thinner layers with distinct functions. The first mask layer (silicon nitride) provides the necessary thickness for preventing short circuits during impurity implantation, while the second mask layer (oxide) provides precise pattern definition. This segmentation achieves reliability without the manufacturing complexity of a single ultra-thick mask layer.
Solution Approach 2:
The mask member is constructed as a composite structure using two different materials: silicon nitride for the first mask layer and oxide for the second mask layer. Each material is selected for its specific properties - silicon nitride provides excellent implantation barrier properties, while oxide provides good etch selectivity for gate electrode formation. This composite approach achieves short circuit prevention while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable punch-through breakdown voltage and prevents short circuits by controlling impurity distribution and mask thickness, resulting in a highly reliable FinFET semiconductor device.
Implementation Method 1
implanting an impurity into the semiconductor substrate with the upper-side mask member and the lower-side mask member as a mask
Data Source
AI summary
According to one embodiment, a method for manufacturing a semiconductor device, includes preparing a structure body. In the structure body, a fin extending in a first direction is formed on an upper surface of a semiconductor substrate, a lower-side mask member is provided on the fin, and an upper-side mask member that is wider than the fin and the lower-side mask member is provided on the lower-side mask member. The method includes implanting an impurity into the semiconductor substrate with the upper-side mask member and the lower-side mask member as a mask, removing the upper-side mask member, forming a gate insulator film on a side surface of the fin, forming a conductive film that covers the fin and the lower-side mask member, forming a mask for gate having a pattern extending in a second direction, and removing selectively the conductive film to form a gate electrode.