Dual-Master Bus Circuit Using Three-State Gate Isolation
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Solution Overview
Problem
In electronic control devices, particularly in the motor vehicle sector, the need for dual microprocessors with multi-master capability increases complexity and risks damage to components due to shared clock signal interference between backup processors.
Innovation Solution
The implementation of three-state gates at the outputs of each master in the bus system, allowing one master to act as a closed switch while the other acts as an open switch, thereby isolating their signals and preventing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual microprocessors with multi-master capability are implemented, then safety and reliability are improved, but device complexity increases
Solution Approach 1:
The bus system is segmented into multiple independent signal lines (clock signal line, master data signal line, slave data signal line, select signal line), allowing each signal type to be managed separately. This segmentation enables the dual microprocessor system to operate reliably without requiring complex multi-master capability in each processor.
2Adaptability or versatility
If both microprocessors deliver clock signals to the shared bus system, then operational flexibility is improved, but harmful interference and component damage occur
Solution Approach 1:
A control unit is introduced as an intermediary that manages clock signal distribution to the bus system. The control unit receives clock signals from both microprocessors and selectively routes them to the bus, preventing direct interference between the processors while maintaining operational flexibility. This mediator approach allows both processors to remain operational without causing signal conflicts.
Data Source
AI summary
An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch.