Dual-Master Flip-Flop Structure for Reduced Set-Up Time
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Solution Overview
Problem
Conventional flip-flop structures in digital circuits face challenges in reducing overall delay time due to the presence of multiplexers, which worsen the CK-Q time and set-up time, making it essential to develop new structures and methods that can minimize these delays.
Innovation Solution
A flip-flop structure is designed with two master latches to separately process function data and scan data, eliminating the need for a multiplexer and reducing set-up time by allowing each latch to operate independently under control signals, thereby minimizing the overall delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiplexers are used in conventional flip-flop structures for multiple inputs or multiple latches, then the device can handle multiple data paths, but the CK-Q time and set-up time increase due to multiplexer delay
Solution Approach 1:
The flip-flop is divided into two independent master latches (first master latch and second master latch) that operate in parallel. Each latch handles different data inputs (function data and scan data respectively) without requiring multiplexing, thereby eliminating multiplexer delay while maintaining the ability to process multiple data paths simultaneously.
Solution Approach 2:
The dual master latch structure provides multi-functionality by enabling the flip-flop to process both function data and scan data through separate latches. This universal structure eliminates the need for multiplexers while maintaining adaptability to different data input types and modes.
2Device complexity
If conventional flip-flop structures are used, then the design is simple and well-established, but the overall delay time is longer due to multiplexer placement
Solution Approach 1:
The flip-flop is segmented into two independent master latches that operate in parallel. This segmentation eliminates the need for multiplexers in the data path, thereby reducing overall delay while maintaining a relatively simple and well-established latch-based structure.
Solution Approach 2:
The patent combines two master latches and a slave latch into a unified flip-flop structure. This merging allows both function data and scan data to be processed simultaneously through parallel latches, reducing overall delay while maintaining structural simplicity.
Data Source
AI summary
A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.