Dual Master JTAG Controller Mode Switching
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Solution Overview
Problem
Modern integrated circuit devices face challenges in testing due to increased density and decreased size, as well as the complexity introduced by customized test circuitry that must comply with the JTAG standard while performing customized testing, leading to increased area occupation and complication of test circuitry.
Innovation Solution
A dual-master controller JTAG test circuitry system that operates in both standard JTAG mode and CPU-to-JDR mode, allowing a central processing unit to control data registers and perform customized testing, with a selection multiplexer and logic circuit to switch between modes based on control signals, thereby simplifying the test circuitry and maintaining compliance with the JTAG standard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If customized test circuitry is included to perform desired custom testing, then testing flexibility is improved, but test circuitry complexity and area occupation increase
Solution Approach 1:
The patent merges the standard JTAG TAP controller and the processor controller into a single dual-master controller entity. This unified controller shares common hardware resources including data registers, instruction decoders, and control logic, allowing both standard JTAG testing and customized processor-controlled testing to be performed by the same integrated circuitry rather than requiring separate independent controllers.
Solution Approach 2:
The dual-master controller is designed with multi-functionality to handle both standard JTAG TAP protocol operations and customized processor-controlled testing operations. The controller can operate in multiple modes depending on which master (JTAG TAP or processor) is active, and includes universal data registers and control logic that serve both testing paradigms, thereby providing testing flexibility without proportionally increasing complexity.
2Adaptability or versatility
If customized test circuitry is included to perform desired custom testing, then testing flexibility is improved, but area occupied by test circuitry increases
Solution Approach 1:
The patent merges the standard JTAG TAP controller and the processor controller into a single dual-master controller entity. This unified controller shares common hardware resources including data registers, instruction decoders, and control logic, allowing both standard JTAG testing and customized processor-controlled testing to be performed by the same integrated circuitry rather than requiring separate independent controllers.
Solution Approach 2:
The dual-master controller is designed with multi-functionality to handle both standard JTAG TAP protocol operations and customized processor-controlled testing operations. The controller can operate in multiple modes depending on which master (JTAG TAP or processor) is active, and includes universal data registers and control logic that serve both testing paradigms, thereby providing testing flexibility without proportionally increasing complexity.
3Adaptability or versatility
If both standard JTAG mode and CPU-to-JDR mode are supported, then testing versatility is improved, but control signal routing complexity increases
Solution Approach 1:
The patent introduces a selection multiplexer as an intermediary component that manages the routing between the two masters (JTAG TAP controller and processor controller) and the shared test circuitry. The multiplexer receives control signals indicating which master should be active and accordingly routes the appropriate control signals to the data registers and other test components, thereby simplifying the overall routing logic compared to having completely separate control paths for each mode.
Solution Approach 2:
The control signal routing is made dynamic through the use of mode selection signals that can change the active master at runtime. The system can switch between JTAG TAP mode and processor-controlled mode as needed, with the selection multiplexer dynamically reconfiguring the signal paths based on the current operational mode, rather than having fixed static routing for each mode.
Data Source
AI summary
A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode. An instruction decoder and multiplexer circuit applies control signals from the selection multiplexer to control the JTAG data registers.