Dual-Material Interconnect Structure for Tight CD Scaling
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) are scaled down, the increased density and reduced spacing between conductive features lead to increased capacitance, which in turn increases power consumption and time delay, posing challenges for manufacturing techniques and device design.
Innovation Solution
The solution involves forming an interconnect structure with two conductive materials, where a first interconnect conductive structure with a critical dimension below a predetermined threshold comprises a first conductive material, and a second interconnect conductive structure with a critical dimension above the threshold comprises an outer portion of the first conductive material surrounding a central portion of a second conductive material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the spacing between conductive features is reduced to increase density, then the IC size is reduced, but the capacitance increases leading to higher power consumption and time delay
Solution Approach 1:
The patent applies local quality by using different conductive materials in different regions of the interconnect structure. Specifically, a first conductive material is used for the outer portion and a second conductive material is used for the central portion, allowing each region to be optimized for its specific function and dimensional requirements, thereby managing capacitance and power consumption locally rather than uniformly across the entire structure
Solution Approach 2:
The patent employs composite materials by combining two different conductive materials within a single interconnect structure. The outer portion uses a first conductive material while the central portion uses a second conductive material, creating a composite structure that leverages the advantages of both materials to reduce capacitance and power consumption while maintaining signal integrity
2Volume of moving object
If the critical dimension of conductive features is reduced to increase density, then the IC size is reduced, but the manufacturing precision and material selection become more challenging
Solution Approach 1:
The patent applies segmentation by dividing the interconnect structure into distinct regions - an outer portion and a central portion - each with different critical dimensions and materials. This segmentation allows independent optimization of each region's manufacturing process, enabling precise control over the critical dimensions of each segment while maintaining overall structure integrity
Solution Approach 2:
The patent utilizes parameter changes by varying the critical dimensions of different portions of the interconnect structure. The outer portion has a first critical dimension while the central portion has a second critical dimension, allowing each portion to be manufactured with appropriate precision levels and material selections suited to its specific dimensional requirements
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate, a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect conductive structure arranged within the second interconnect dielectric layer. The interconnect conductive structure includes an outer portion that includes a first conductive material. Further, the interconnect conductive structure includes a central portion having outermost sidewalls surrounding by the outer portion of the interconnect conductive structure. The central portion includes a second conductive material different than the first conductive material.