Dual-Material Self-Aligned Patterning for Cut-Hole Yield
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Solution Overview
Problem
Existing self-aligned quadruple and octuple patterning processes in IC lithography suffer from edge-placement errors due to overlay misalignment and critical-dimension variations, leading to yield loss and potential device failure, as they typically use single-material final line features that cannot accommodate selective etching to avoid cutting non-targeted lines.
Innovation Solution
Developing dual-material self-aligned quadruple (dmSAQP) and octuple (dmSAOP) patterning processes, where multiple spacers and mandrels are formed using different materials, allowing for highly selective etching to accurately cut targeted lines without damaging non-targeted ones, and employing mask design techniques to decompose holes into smaller features that expose only one material at a time for precise etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single-material self-aligned quadruple and octuple patterning processes are used, then the fabrication process is simpler, but edge-placement errors occur due to overlay misalignment and critical-dimension variations, leading to yield loss
Solution Approach 1:
The patent applies local quality by using different materials (first material and second material) for different line features in the final pattern. This allows selective etching where only lines made of the first material are removed, while lines made of the second material are preserved. The material differentiation at the local level enables precise control over which features are etched, resolving the edge-placement accuracy issue without requiring perfect overlay alignment.
Solution Approach 2:
The patent employs composite materials by creating line features composed of two distinct materials through the dual-material self-aligned multiple patterning process. The first spacers are made of a first material while the second spacers are made of a second material, resulting in final line features that can be selectively etched based on their material composition. This composite material approach enables the selective removal of certain lines while preserving others, directly addressing the yield loss problem.
2Ease of manufacture
If single-material final line features are used, then the patterning process is easier to implement, but selective etching cannot be performed to avoid cutting non-targeted lines
Solution Approach 1:
The patent applies local quality by using different materials (first material and second material) for different line features in the final pattern. This allows selective etching where only lines made of the first material are removed, while lines made of the second material are preserved. The material differentiation at the local level enables precise control over which features are etched, resolving the edge-placement accuracy issue without requiring perfect overlay alignment.
Solution Approach 2:
The patent employs composite materials by creating line features composed of two distinct materials through the dual-material self-aligned multiple patterning process. The first spacers are made of a first material while the second spacers are made of a second material, resulting in final line features that can be selectively etched based on their material composition. This composite material approach enables the selective removal of certain lines while preserving others, directly addressing the yield loss problem.
3Productivity
If overlay errors and critical-dimension variations are present in cut-hole patterning, then the patterning process can be performed, but yield loss occurs due to inaccurate edge placement
Solution Approach 1:
The patent applies local quality by using different materials (first material and second material) for different line features in the final pattern. This allows selective etching where only lines made of the first material are removed, while lines made of the second material are preserved. The material differentiation at the local level enables precise control over which features are etched, resolving the edge-placement accuracy issue without requiring perfect overlay alignment.
Solution Approach 2:
The patent employs composite materials by creating line features composed of two distinct materials through the dual-material self-aligned multiple patterning process. The first spacers are made of a first material while the second spacers are made of a second material, resulting in final line features that can be selectively etched based on their material composition. This composite material approach enables the selective removal of certain lines while preserving others, directly addressing the yield loss problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-material approach significantly reduces edge-placement errors, enhancing the accuracy and yield of the cut-hole patterning process by enabling selective etching that avoids material loss and ensures precise cutting of targeted lines, thereby improving the reliability of IC fabrication.
Implementation Method 1
highly selective etching process to remove certain type of lines (e.g., made of material A) with negligible loss of the other lines (e.g., made of material B)
Data Source
AI summary
Design and fabrication methods to reduce the effect of edge-placement errors in the cut-hole patterning process are invented using selective etching and dual-material self-aligned multiple patterning processes. The invented methods consist of a series of processing steps to decompose the original cut-hole mask into multiple separate masks, pattern the cut holes on the resist to expose certain targeted lines, and selectively etch the exposed targeted lines (formed by dual-material self-aligned multiple patterning processes) without attacking the non-target lines. This invention provides production-worthy methods for the semiconductor industry to continue IC scaling down to sub-10 nm half pitch.