Dual-Material Via Contacts for Low-Resistance Semiconductor Interconnects
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices leads to deterioration in operational properties, necessitating the development of technologies that can reduce resistance and facilitate the formation of via contacts and overlay keys with varying widths simultaneously.
Innovation Solution
A semiconductor device design that incorporates via contacts with reduced resistance, where the first via contact has a narrower width and the second via contact has a wider width, both formed using a combination of metal patterns with different materials, allowing for simultaneous formation with overlay key patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to reduce pattern size and design rule, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent applies local quality by providing different via contact widths for different functional regions. The first via contact has a first width for connecting to the first upper conductive pattern, while the second via contact has a second width (different from the first width) for connecting to the second upper conductive pattern. This allows optimization of electrical properties locally according to specific connection requirements, thereby improving operational performance without requiring uniform scaling across all structures.
2Length of moving object
If via contacts are formed with reduced width to meet scaling requirements, then pattern density is improved, but electrical resistance increases
Solution Approach 1:
The patent implements local quality by assigning different widths to different via contacts based on their specific electrical requirements. The second via contact has a second width that is different from the first width of the first via contact, allowing the second via contact to have optimized resistance characteristics for its specific connection while maintaining overall pattern density improvements from scaling.
3Productivity
If via contacts and overlay key patterns with different widths are formed simultaneously, then manufacturing process efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies merging by combining the formation of via contacts and overlay key patterns into a single manufacturing process step. The lower conductive patterns, upper conductive patterns, via contacts with different widths, and overlay key patterns are all formed simultaneously, which improves manufacturing efficiency and reduces the number of process steps while maintaining the required width variations through integrated patterning.
Data Source
AI summary
A semiconductor device includes lower conductive patterns on a substrate and horizontally spaced apart from each other, upper conductive patterns on the lower conductive patterns and horizontally spaced apart from each other, and a first via contact and a second via contact between the lower and upper conductive patterns and horizontally spaced apart from each other. The first via contact has a first width in a direction parallel to a top surface of the substrate. The second via contact has a second width in the direction that is wider than the first width. The second via contact includes a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern includes a same material as the first via contact, and the second metal pattern includes a different material from the first metal pattern and the first via contact.