Dual Memorization Layer for Multi-Color Spacer Patterning
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Solution Overview
Problem
Conventional self-aligned multiple patterning (SAMP) processes damage the low-k interlayer dielectric layer during the formation of trenches and vias, compromising its electrical properties.
Innovation Solution
The introduction of a trench memorization layer and a via memorization layer between the multi-color spacer patterning structures and the low-k interlayer dielectric layer, which allows for the formation of trenches and vias without damaging the low-k properties by using these layers as etch masks and protecting the underlying dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SAMP processes are used to form trenches and vias, then the patterning function is achieved, but the low-k interlayer dielectric layer is damaged and its electrical properties are compromised
Solution Approach 1:
The patent introduces memorization layers as intermediary structures between the spacer patterning structures and the low-k interlayer dielectric layer. These memorization layers serve as protective intermediaries that absorb the harmful effects of the etching process, preventing direct damage to the low-k layer while still enabling precise trench and via formation through the spacer release holes.
Solution Approach 2:
The memorization layers are formed in advance before the trench and via etching process. By pre-positioning these protective layers, the patent ensures that the low-k interlayer dielectric layer is already protected before the harmful etching actions occur, thereby preventing damage while maintaining patterning precision.
2Ease of manufacture
If etching is performed directly on the low-k interlayer dielectric layer to form trenches and vias, then the desired structures are created, but surface damage occurs compromising the low-k properties
Solution Approach 1:
The memorization layers act as intermediary protective barriers during the etching process. They allow the etching to proceed easily to form trenches and vias while mediating the interaction between the etch process and the low-k layer, preventing direct contact and damage that would compromise electrical properties.
Solution Approach 2:
The memorization layers provide beforehand cushioning protection to the low-k interlayer dielectric layer. By placing these sacrificial protective layers in position prior to etching, they cushion against the harmful effects of the etching process, allowing easy manufacture of trenches and vias without damaging the underlying low-k layer's electrical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of trenches and vias in the low-k interlayer dielectric layer without damaging its properties, maintaining the integrity of the low-k characteristics and avoiding the surface damage seen in prior art techniques.
Implementation Method 1
The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer
Data Source
AI summary
A self-aligned multiple patterning (SAMP) multi-color spacer patterning process is disclosed for formation of structures on substrates. Trenches and vias may be formed in the process. A trench memorization layer and a via memorization layer may be formed on the substrate. In one embodiment, the trench memorization layer and the via memorization layer are formed between the multi-color spacer patterning structures and a low-k interlayer dielectric layer. The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer.