Dual Memory Bitcell Shared Virtual Ground Layout
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Solution Overview
Problem
Conventional memory bitcell designs in modern nano process technology face limitations such as increased track/signal limitations, inflexibility in transistor characteristics, and wasteful use of area due to dummy transistors, particularly in achieving balanced true/false node structures and accommodating Layout Proximity Effect.
Innovation Solution
Implementing a dual memory bitcell with a shared virtual ground line that operates as a function of the write bitline, reducing power consumption and area requirements, and allowing for a novel physical layout with fewer dummy transistors, enabling efficient storage and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bitcell designs use a dual bitline scheme to ensure writability, then writability is improved, but area increases due to dummy transistors being added to accommodate bitcell area dictated by wiring tracks
Solution Approach 1:
The patent merges the ground reference function into the bitline itself by making the bitline toggle between representing logic 0 and logic 1 based on its relationship to the virtual ground. This eliminates the need for separate ground references and dummy transistors, reducing area while maintaining writability through the dual-state bitline mechanism.
Solution Approach 2:
The patent extracts the ground reference function from the traditional ground line and integrates it into the bitline signaling mechanism. By taking out the explicit ground reference and incorporating it into the bitline's state representation, the design eliminates unnecessary dummy transistors and reduces overall area.
2Stability of the object's composition
If conventional bitcell designs seek a balanced structure of true/false nodes, then symmetry is improved, but flexibility in choosing transistor characteristics is limited
Solution Approach 1:
The patent introduces asymmetry in the bitline configuration by making the bitline's relationship to the virtual ground determine its logic state rather than requiring symmetric true/false node structures. This asymmetric approach allows greater flexibility in transistor selection and characteristics while maintaining stable memory cell operation through the virtual ground reference.
3Area of stationary object
If bitcell layouts are packed as tightly as possible, then area density is improved, but dummy transistors are still added to fulfill LPE which is a waste of area
Solution Approach 1:
The patent takes out the dummy transistor requirement by extracting the LPE fulfillment function and integrating it into the virtual ground switching mechanism. The virtual ground switch dynamically adjusts the reference potential to satisfy LPE requirements without needing actual dummy transistors, eliminating area waste while maintaining layout density.
Data Source
AI summary
Embodiments include systems and methods for using a shared virtual ground to implement a dual memory bitcell. Some embodiments of the dual memory bitcell described herein operate substantially as would two adjacent conventional bitcells, but with reduced power, reduced area, and other features. For example, each of two memory bitcells can be coupled with a write bitline, a virtual ground line, and a respective write wordline. The virtual ground is configured to be switched according to the write bitline. In such a configuration, the value stored by the memory bitcells can be a function of the write bitline and the virtual ground line (e.g., when the respective write word line of the memory bitcell is asserted). Certain embodiments can include a novel physical layout of the dual memory bitcell. Some implementations of the novel physical layout can include changes to the physical memory bitcell components and to one or more metal layers.