Dual Memory Block Flash with Distinct Read Voltages
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Solution Overview
Problem
Flash memory technologies face challenges in providing adequate read disturbance immunity for code flash memory applications, which are prone to data corruption due to higher read operations and lower program/erase cycles, while also requiring efficient operation for data flash memory applications with frequent updates.
Innovation Solution
An integrated circuit with two memory blocks, each configured for different patterns of data usage, employs distinct operation algorithms and word line pass voltages to maintain read disturbance immunity for code flash while allowing lower endurance cycles, and higher read disturbance for data flash, using the same memory cell structure with incremental step pulse programming to adjust pass voltages and program biases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same memory cell structure is used for both code flash and data flash, then device complexity is reduced, but read disturbance immunity deteriorates for code flash applications
Solution Approach 1:
The patent applies local quality by implementing different operation algorithms for different memory blocks. Code flash memory blocks use a first operation algorithm with lower pass voltages to minimize read disturbance, while data flash memory blocks use a second operation algorithm with higher pass voltages for efficient programming. This allows the same physical memory cell structure to serve different functional requirements with optimized characteristics for each application type.
2Reliability
If lower pass voltages are used for read operations in code flash, then read disturbance immunity is improved, but programming efficiency deteriorates
Solution Approach 1:
The patent segments the memory device into multiple memory blocks that can be independently configured for different operation algorithms. This segmentation allows code flash blocks to use conservative read voltages for high reliability while data flash blocks can use aggressive programming voltages for high speed, eliminating the need to compromise either read disturbance immunity or programming efficiency across the entire device.
3Adaptability or versatility
If multiple memory blocks with different operation algorithms are implemented, then adaptability to different data usage patterns is improved, but device complexity increases
Solution Approach 1:
The patent implements universality by designing memory blocks that can operate under multiple operation algorithms. The same physical memory cell structure supports both code flash operation (with lower pass voltages and different programming parameters) and data flash operation (with higher pass voltages and optimized programming sequences), allowing a single device to serve multiple data usage patterns without requiring entirely separate memory structures.
Data Source
AI summary
An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.