Dual Memory Chip Package Heterogeneous Addressing
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Solution Overview
Problem
Existing dual-chip packages struggle to access memory chips with different address systems, particularly when both RAM and flash memory are included, as the option pads cannot distinguish between them, limiting selective access.
Innovation Solution
A dual-chip package design that includes shared pins, buffer and flash memory chips, option pads connected to different voltages, registers to store flag signals, and a comparator circuit to generate access signals, allowing controllers to manage access between buffer and flash memories based on programmed flags.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If option pads are used to distinguish between top and bottom memory chips, then chip selection is enabled, but selective access to different memory types (RAM and flash memory) within the same chip is not possible
Solution Approach 1:
The address space is segmented into two distinct parts: option pad bits for chip-level selection (top/bottom) and address bits for memory-type selection (RAM/flash memory). This segmentation allows the system to independently address different hierarchical levels of memory organization, enabling both chip selection and memory type differentiation simultaneously.
Solution Approach 2:
The patent introduces an additional addressing dimension by incorporating address bits that operate independently from the option pad bits. While option pads provide one dimension of selection (chip level), the address bits provide a second dimension (memory type level), creating a two-dimensional addressing space that enables comprehensive memory access control.
2Device complexity
If multiple memory chips are packaged together to increase capacity and reduce size, then integration is improved, but the ability to access memories with different address systems becomes difficult
Solution Approach 1:
The controller is designed with universal addressing capabilities that can handle multiple memory types (RAM and flash memory) with different address systems. The controller interprets address bits universally across both memory types, allowing a single controller to manage heterogeneous memory chips without requiring type-specific control logic for each chip.
Solution Approach 2:
The address bits act as an intermediary mechanism between the external interface and the internal memory structures. These address bits translate external address signals into appropriate internal selections, mediating between the unified external interface and the diverse internal memory types with different address systems.
3Device complexity
If the same address system is used for all memory chips, then addressing is simplified, but the ability to support different memory types with different address systems is lost
Solution Approach 1:
The patent applies local quality by allowing different memory types within the same chip to have different address system characteristics. The address bits are interpreted differently depending on which memory type is selected, enabling each memory type to operate with its native address system while maintaining a unified external interface.
Solution Approach 2:
The system dynamically changes addressing parameters based on memory type selection. When a specific memory type is selected via address bits, the addressing mode and interpretation rules change accordingly, allowing the system to adapt between different address systems (RAM addressing vs. flash memory addressing) without requiring separate physical interfaces.
Data Source
AI summary
A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may include a register for storing first and second flag signals each indicative of selections of corresponding memory chips, a comparator circuit for comparing the first and second flag signals in the register with a reference signal to generate a flash access signal and a buffer access signal, and a controller for controlling the buffer memory and the flash memory in response to the flash access signal and the buffer access signal.