Dual Memory Package Chip Select Wiring for Shorter PCB Traces

Solution Overview

Problem

In dual device packages, the conventional chip select (CS) wiring results in longer trace lengths due to swapped pin locations for back-to-back memory devices, leading to lower signal quality and inefficient processing.

Innovation Solution

The proposed solution involves coupling CS signal lines with both upper and lower memory dies, using vias to connect the signal lines directly to the corresponding pins, thereby reducing trace lengths and improving signal integrity by wiring based on physical location rather than logical pin number.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional chip select wiring is used with swapped pin locations for back-to-back memory devices, then both memory devices can be connected to the circuit board, but the trace lengths become longer resulting in lower signal quality

Engineering Contradiction:

Improvesignal qualityVSAvoidtrace length

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent inverts the conventional wiring approach by not swapping pin locations for back-to-back memory devices. Instead of following the traditional method where pin locations are swapped, the invention uses identical pin locations for both devices, which shortens the trace lengths and improves signal quality while maintaining the ability to independently select each memory device through different chip select signals.

Inventive Principle:

Principle #13The other way round (Inversion)

2Productivity

If conventional chip select wiring with swapped pin locations is used, then both memory devices can be addressed, but the processing efficiency decreases due to longer trace lengths

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidtrace length

Core Design Contradiction:

ProductivityVSLength of stationary object

Solution Approach 1:

The patent inverts the conventional wiring approach by not swapping pin locations for back-to-back memory devices. Instead of following the traditional method where pin locations are swapped, the invention uses identical pin locations for both devices, which shortens the trace lengths and improves signal quality while maintaining the ability to independently select each memory device through different chip select signals.

Inventive Principle:

Principle #13The other way round (Inversion)

3Reliability

If trace lengths are reduced by changing wiring configuration, then signal quality improves, but additional space becomes available for other components

Engineering Contradiction:

Improvesignal integrityVSAvoidavailable space

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent inverts the conventional wiring approach by not swapping pin locations for back-to-back memory devices. Instead of following the traditional method where pin locations are swapped, the invention uses identical pin locations for both devices, which shortens the trace lengths and improves signal quality while maintaining the ability to independently select each memory device through different chip select signals.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20240178149A1Chip select wiring for a dual device package

Publication Date: 2024.05.30 MICRON TECHNOLOGY INC

AI summary

Methods, systems, and devices for chip select wiring for a dual device package are described. A circuit board includes a plurality of layers, the plurality of layers including a first outer layer, a second inner layer, and a third outer layer. The circuit board also includes first and second chip select (CS) signal lines routed through the second inner layer of the circuit board, first and second memory devices coupled with the first outer layer and the third outer layer, respectively, a first via coupling the first CS signal line with a first upper memory die of the first memory device and a second lower memory die of the second memory device, and a second via coupling the second CS signal line with a second upper memory die of the second memory device and a first lower memory die of the first memory device.