Dual Memory Clock Drivers to Eliminate Word Line Delay

Solution Overview

Problem

Memory devices with a single memory clock driver suffer from contamination delay issues, leading to timing errors and reduced speed, as the voltage change propagates across the word line, affecting the activation of memory cells, especially at distances far from the driver, resulting in potential errors or the need to operate at lower speeds to prevent errors.

Innovation Solution

Implementing a second memory clock driver opposite the first one on the memory clock line to pull both sides of the line to the desired voltage, eliminating contamination delay by ensuring simultaneous activation of word lines at both ends.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single memory clock driver is used, then device complexity is reduced, but propagation delay increases causing timing errors

Engineering Contradiction:

Improvememory clock driver configurationVSAvoidpropagation delay

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The memory clock line is segmented into two sections with drivers placed at opposite ends (first end and second end), allowing simultaneous driving of the clock signal in opposite directions to eliminate propagation delay across the entire line length

Inventive Principle:

Principle #1Segmentation

2Device complexity

If a single memory clock driver is used, then device complexity is reduced, but timing accuracy deteriorates due to contamination delay

Engineering Contradiction:

Improvememory clock driver configurationVSAvoidtiming accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The memory clock line is segmented into two sections with drivers placed at opposite ends (first end and second end), allowing simultaneous driving of the clock signal in opposite directions to eliminate propagation delay across the entire line length

Inventive Principle:

Principle #1Segmentation

3Device complexity

If a single memory clock driver is used, then device complexity is reduced, but operational speed must be reduced to prevent errors

Engineering Contradiction:

Improvememory clock driver configurationVSAvoidoperational speed

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The memory clock line is segmented into two sections with drivers placed at opposite ends (first end and second end), allowing simultaneous driving of the clock signal in opposite directions to eliminate propagation delay across the entire line length

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12009055B2Far end driver for memory clock

Publication Date: 2024.06.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Memory clock drivers, memories, and methods of operating memory clock drivers are provided. A memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. The memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. The decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. The memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. The memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as I/O modules to send signals to different parts of the memory device and integrate the memory device into external devices.