Dual Memory Clock Driver Layout for Word Line Timing Accuracy
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Solution Overview
Problem
Memory devices with a single memory clock driver suffer from contamination delay, leading to timing issues and errors in high-speed applications due to the delay in activating word lines, especially at the ends far from the driver, which can result in incorrect data storage or require slower operation speeds to prevent errors.
Innovation Solution
Implementing a second memory clock driver at the opposite end of the memory clock line from the first driver to eliminate contamination delay by ensuring both ends of the word line are activated simultaneously, reducing propagation delay and error risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single memory clock driver is used to activate word lines, then the device complexity is reduced, but contamination delay occurs leading to timing errors in high-speed applications
Solution Approach 1:
The patent divides the single memory clock driver into two separate drivers positioned at opposite ends of the memory clock line. This segmentation allows each driver to independently activate word lines from its respective end, eliminating the contamination delay that occurs when a single driver must propagate signals across the entire line length.
2Loss of time
If a single memory clock driver is used, then the propagation delay is minimized in terms of driver count, but timing errors occur at word line ends far from the driver
Solution Approach 1:
The patent introduces a spatial dimension by positioning two drivers at opposite ends of the memory clock line rather than concentrating activation at a single point. This dimensional change allows simultaneous activation from both ends, reducing the maximum propagation distance and eliminating timing errors at distant word lines.
3Reliability
If memory operations are slowed down to prevent timing errors, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent performs preliminary activation of word lines from both ends simultaneously before the contamination delay can affect high-speed operations. By pre-establishing the clock signal at both ends of the memory clock line, the system maintains timing accuracy even at high operation speeds without requiring speed reduction.
Data Source
AI summary
Memory clock drivers, memories, and methods of operating memory clock drivers are provided. A memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. The memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. The decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. The memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. The memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as I/O modules to send signals to different parts of the memory device and integrate the memory device into external devices.