Dual Memory Controller Subsystem for Automotive Error Detection
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Solution Overview
Problem
Future generation processing systems, particularly in automotive applications, face increased complexity due to growing functionalities and tight execution constraints, requiring improved flexibility and efficient interfacing with external memories while meeting safety and security standards.
Innovation Solution
A processing system with a memory controller subsystem that includes dual memory controllers and a switching mechanism to manage communication with external memories, supporting multiple operating modes for error detection and correction, ensuring reliable data transmission and compliance with Automotive Safety Integrity Levels (ASIL) standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single memory controller is used to interface external memory, then the device complexity is low, but the reliability and error detection capability are insufficient
Solution Approach 1:
The memory controller is divided into two independent controllers (first memory controller and second memory controller), each capable of independently interfacing with the external memory. This segmentation allows parallel operation for error detection while maintaining individual controller functionality, resolving the contradiction between reliability improvement and complexity increase.
Solution Approach 2:
A second memory controller is implemented as a duplicate of the first memory controller to create redundancy. The second controller copies the interfacing functionality of the first controller, enabling comparison-based error detection. This copying approach improves reliability through redundancy while keeping each controller unit relatively simple.
2Reliability
If dual memory controllers are implemented for error detection, then the reliability improves, but the device complexity increases
Solution Approach 1:
A switching mechanism is introduced as an intermediary component that manages the interaction between the two memory controllers and the external memory. The switch routes signals appropriately and coordinates the operation of both controllers, enabling error detection functionality while abstracting the complexity from the overall system architecture.
Solution Approach 2:
The system dynamically switches between different operating modes (first operating mode with first controller only, second operating mode with second controller only, third operating mode with both controllers for error detection). This dynamic configuration allows the system to adapt reliability and complexity levels based on operational requirements, resolving the static contradiction between reliability and complexity.
3Adaptability or versatility
If multiple operating modes are supported for error detection, then the adaptability improves, but the ease of operation decreases
Solution Approach 1:
The system implements periodic self-testing operations where the two memory controllers alternately or simultaneously perform error detection cycles. This periodic action enables automatic error detection without requiring continuous manual configuration, improving adaptability while maintaining ease of operation through automated testing sequences.
Data Source
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AI summary
A processing system (10a) is described. A memory controller subsystem (50a) is connected to a communication channel (EXT1, EXT2) configured to be connected to an external memory (42a), wherein the communication channel (EXT1, EXT2) comprises a data signal (IO). A master circuit (54; 102, 110) is configured to send write and read requests to the memory subsystem (50a). The memory controller subsystem (50a) comprises a first memory controller (500a) and a second memory controller (500b). In response to receiving a write request, each memory controller generates a respective first or second communication (EXTa, EXTb) for storing the respective data (DATA_INa, DATA_INb) to the respective memory address (ADRa, ADRb) by generating a respective first or second data signal (IOa, IOb) used to transmit the respective memory address (ADRa, ADRb) and the respective data (DATA INa, DATA_INb). Conversely, in response to receiving a read request, each memory controller generates the respective first or second communication (EXTa, EXTb) for receiving data (DATA_OUTa, DATA_OUTb) associated with the respective memory address (ADRa, ADRb) by generating the respective first or second data signal (IOa, IOb) to transmit the respective memory address (ADRa, ADRb) and receive the respective data (DATA OUTa, DATA_OUTb). Moreover, each memory controller generates a respective first or second response comprising the respective received data (DATA_OUTa, DATA OUTb). Specifically, in a first operating mode, the first memory controller (500a) is used to interface an external memory (42a), and the second memory controller (500b) is used to verify the correct operation of the first memory controller (500a), e.g., by comparing (5040; 5046) the first data signal (IOa) with the second data signal (IOb) and comparing (5048, 5050) the first response with the second response.