Dual-Memory Image Processing Circuit for Low-Power Frame Transfer

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Solution Overview

Problem

The second memory in conventional image processing circuits remains active during image writing, leading to excessive power consumption and a decline in user experience.

Innovation Solution

Implementing a first and second memory with different operating speeds, where the image processing circuit operates in a low-speed mode during image reception and storage in the first memory, and switches to a high-speed mode for transferring images from the first memory to the second memory, reducing overall power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the second memory remains in active state during image writing, then the image can be written into the second memory, but the power consumption increases excessively

Engineering Contradiction:

Improveimage writing completenessVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by switching the second memory between active and low-power states based on operational phase. During image writing, the second memory is activated to receive data; during vertical blank intervals, it transitions to a low-power state. This dynamic state change resolves the contradiction by maintaining reliability during writing while reducing power consumption during idle periods.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action by utilizing the vertical blank interval between image frames to switch the second memory to a low-power state. This periodic switching between active and low-power modes during each frame cycle allows complete image writing while significantly reducing overall power consumption, resolving the technical contradiction.

Inventive Principle:

Principle #19Periodic action

2Productivity

If the image processing circuit operates in high-speed mode continuously, then the image processing speed is fast, but the power consumption increases

Engineering Contradiction:

Improveimage processing speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by alternating between high-speed mode during active image writing and low-speed mode during vertical blank intervals. This periodic switching maintains high image processing speed when needed while reducing power consumption during idle periods, effectively resolving the contradiction between productivity and energy use.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent implements dynamics by making the operating speed adjustable between high-speed and low-speed modes based on the processing phase. The system dynamically switches modes: high-speed during image data transfer, low-speed during vertical blank intervals, thereby achieving both high productivity when required and low power consumption during idle time.

Inventive Principle:

Principle #15Dynamics

3Speed

If the second memory operates at high speed continuously, then the write speed is fast, but the power consumption increases

Engineering Contradiction:

Improvememory write speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by switching the second memory between high-speed operation during image writing and low-power state during vertical blank intervals. This periodic switching maintains fast write speed during data transfer while dramatically reducing power consumption during idle periods, resolving the contradiction between speed and energy consumption.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent implements dynamics by making the second memory's operating speed adjustable between high-speed and low-power states based on operational requirements. The memory operates at high speed during active writing phases and transitions to low-power state during vertical blank intervals, achieving both fast write performance and low power consumption.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20260004385A1Image processing circuit and operation method thereof

Publication Date: 2026.01.01 SIGMASTAR TECH LTD

AI summary

An image processing circuit is coupled to an image sensor and includes a first memory, a second memory, an image receiving circuit, and a memory access circuit. The image receiving circuit is configured to receive an image from the image sensor and store the image in the first memory. The memory access circuit is configured to write the image from the first memory into the second memory. When the image receiving circuit stores the image in the first memory, the image processing circuit operates in a low-speed mode, and when the memory access circuit writes the image from the first memory into the second memory, the image processing circuit operates in a high-speed mode. The first operating speed of the second memory in the low-speed mode is lower than the second operating speed of the second memory in the high-speed mode.