Dual Memory Image Correction for Projector Distortion
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Solution Overview
Problem
In projector systems, image distortion correction using non-integer offset vectors requires accessing multiple memory locations, leading to increased processing time and cost due to the need for high-speed clock generation.
Innovation Solution
The implementation of a dual-memory section system where data for image correction is stored in multiple memory areas, allowing for efficient data retrieval without the need for high-speed clock access by utilizing cache memory and strategically allocating data across memory sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data of four pixels is read from memory using non-integer offset vectors, then image correction accuracy is improved, but memory access time increases four times compared to integer offset cases
Solution Approach 1:
The memory is divided into multiple memory sections, each storing data of adjacent pixels. This segmentation allows the correction section to read data from different memory sections in parallel, reducing the total memory access time while maintaining the ability to access four pixels for accurate correction.
Solution Approach 2:
Data of adjacent pixels is pre-stored in multiple memory sections before the correction process. This preliminary storage arrangement enables the correction section to quickly retrieve needed data without performing sequential memory accesses, thereby reducing access time while maintaining correction accuracy.
2Productivity
If high-speed clock is used for memory access to reduce data retrieval time, then processing speed is improved, but device cost increases
Solution Approach 1:
By segmenting the memory into multiple sections that store adjacent pixel data, the system can retrieve needed data faster without increasing clock speed. This approach achieves improved processing speed through architectural optimization rather than hardware speed-up, thereby avoiding the cost increase associated with high-speed clocks.
Solution Approach 2:
Multiple memory sections act as intermediaries between the correction section and the main memory. These intermediate storage locations enable faster data retrieval by reducing the distance and complexity of memory accesses, achieving speed improvement without requiring high-speed clock generation circuitry.
3Loss of time
If multiple memory sections are used to store adjacent pixel data, then data retrieval time is reduced, but device complexity increases
Solution Approach 1:
The multiple memory sections serve multiple functions: they store adjacent pixel data, enable parallel data retrieval, and support both integer and non-integer offset vector corrections. This multi-functionality justifies the added complexity by providing versatile performance benefits across different correction scenarios.
Solution Approach 2:
Instead of creating entirely new hardware, the patent uses multiple memory sections that copy and store data of adjacent pixels in a structured manner. This copying approach achieves faster data retrieval through parallel access patterns while adding manageable complexity compared to fundamental hardware redesign.
Data Source
AI summary
An image processing device includes: a first memory section that has memory areas equivalent to data of k1 rows of an image and stores data of at least two adjoining pixels in each of the memory areas; a second memory section that has memory areas equivalent to data of k2 rows of the image and stores data of at least two adjoining pixels in a row different from pixels of which data is stored in the first memory section in each of the memory areas; and a correction section that corrects data of an object pixel, out of pixels of r rows×c columns, using data of a plurality of pixels stored in a memory area corresponding to a position designated by an offset vector corresponding to the object pixel in the first and second memory sections.