Dual Memory Protection Units for Virtualized Real-Time Systems

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Solution Overview

Problem

Existing data processing systems face challenges in maintaining deterministic behavior and timely processing due to the introduction of delays from virtual addressing, particularly in real-time systems, which can compromise performance and increase costs.

Innovation Solution

The implementation of a dual memory protection unit system, where a first memory protection unit enforces permissions for a guest real-time operating system using physical addresses, and a second memory protection unit enforces permissions for a hypervisor, allowing for virtualization of real-time processors while maintaining acceptable processing speeds and responsiveness, thereby avoiding unbounded delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If virtual addressing is used in real-time systems, then memory management flexibility is improved, but processing time increases due to translation lookaside buffer misses and page table walking delays

Engineering Contradiction:

Improvememory management flexibilityVSAvoidprocessing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the memory protection function into two separate hardware units: a first memory protection unit for the guest real-time operating system and a second memory protection unit for the hypervisor. This segmentation allows each unit to operate independently with physical addresses, eliminating the need for virtual-to-physical address translation while maintaining memory management flexibility through hierarchical permission enforcement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a dual memory protection unit structure that acts as an intermediary between the guest operating system and the hypervisor. The first memory protection unit enforces permissions for the guest OS, while the second memory protection unit enforces permissions for the hypervisor, both operating directly on physical addresses without requiring address translation, thus eliminating translation delays.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If virtualization is implemented for real-time processors, then cost is reduced by avoiding separate processors, but deterministic behavior may be compromised

Engineering Contradiction:

Improvenumber of processorsVSAvoiddeterministic behavior

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the permission enforcement functionality into two distinct hardware units that operate in parallel. The first memory protection unit handles guest OS permissions while the second handles hypervisor permissions, both using physical addresses directly. This segmentation enables deterministic behavior by eliminating address translation overhead while allowing cost-effective virtualization through shared hardware resources.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the traditional virtual addressing mechanism (which relies on software-based page table walking) with a hardware-based dual memory protection unit system that directly enforces permissions on physical addresses. This substitution eliminates the mechanical delays of address translation while maintaining the virtualization capability, ensuring deterministic real-time behavior.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Device complexity

If a single memory protection unit is used, then device complexity is reduced, but security and permission enforcement capability are insufficient for both guest OS and hypervisor

Engineering Contradiction:

Improvenumber of memory protection unitsVSAvoidpermission enforcement capability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent divides the memory protection functionality into two specialized units: the first memory protection unit dedicated to enforcing guest OS permissions and the second memory protection unit dedicated to enforcing hypervisor permissions. This segmentation provides fine-grained security control for each layer while maintaining manageable complexity through clear functional separation and direct physical address operation.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9747052B2Virtualisation supporting guest operating systems using memory protection units to determine permission of a memory access operation for a physical address

Publication Date: 2017.08.29 ARM LTD

AI summary

A processor is provided with a first memory protection unit applying a first set of permissions and a second memory protection unit applying a second set of permissions. A memory access will only be permitted if both the first set of permissions and the second set of permissions are satisfied. The processor also includes a memory management unit which serves to translate from virtual addresses VA to physical addresses PA. A selectable one of the first memory protection unit and the memory management unit is active at any given time under control of a selection bit set by a hypervisor program executing at an exception level with higher privilege than the exception level at which the guest operating systems execute.