Dual-Metal Bitline Memory Cell Array for In-Situ Neural Computing
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Solution Overview
Problem
Existing hardware technologies for artificial neural networks lack adequate energy efficiency and are bulky due to the high number of synapses required for high computational parallelism, which is not efficiently addressed by digital supercomputers or CMOS analog circuits.
Innovation Solution
Utilization of non-volatile memory arrays with individually programmable, continuously analog-programmable memory cells to form synapses in neural networks, eliminating the need for separate multiplication and addition logic circuits and enhancing power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or CMOS analog circuits are used to implement neural networks, then computational parallelism can be achieved, but energy efficiency deteriorates and hardware bulkiness increases
Solution Approach 1:
The patent merges memory and computation functions into a single integrated structure where memory cells directly perform synaptic operations. The memory cell array serves both as storage for weight values and as the computational engine for matrix-vector multiplication, eliminating the need for separate multiplication and addition logic circuits.
Solution Approach 2:
The memory cells are designed to perform multiple functions: storing weight values, performing analog multiplication of inputs by weights, and summing results. This multi-functionality allows the same hardware structure to handle both data storage and computational operations that traditionally required separate dedicated circuits.
2Productivity
If digital supercomputers or CMOS analog circuits are used to implement neural networks, then computational parallelism can be achieved, but hardware bulkiness increases
Solution Approach 1:
The patent merges memory and computation functions into a single integrated structure where memory cells directly perform synaptic operations. The memory cell array serves both as storage for weight values and as the computational engine for matrix-vector multiplication, eliminating the need for separate multiplication and addition logic circuits.
Solution Approach 2:
The patent transitions from digital binary representations to analog continuous values, adding a dimensional aspect to the computation. Weight values and input signals are represented by continuous analog quantities (voltages or currents), enabling multiplication and addition to occur naturally through analog circuit behavior rather than discrete digital operations.
3Use of energy by moving object
If non-volatile memory arrays are used for synapses, then energy efficiency and integration are improved, but precise tuning of synapse weights becomes more challenging
Solution Approach 1:
The patent employs continuous analog programming to adjust the threshold voltage of memory cells, enabling precise control of synaptic weights. By varying the threshold voltage parameter continuously rather than in discrete steps, the system achieves fine-grained weight tuning capability.
Solution Approach 2:
The patent implements verify-read operations where the programmed weight values are read back and verified against target values. This feedback mechanism allows iterative adjustment of programming parameters to achieve the desired precision in synapse weight tuning.
Data Source
AI summary
In one example, a system comprises an array of memory cells arranged in rows and columns, the array comprising bitlines coupled to respective columns in the array, respective bitlines comprising a sensing bitline metal layer and a current-carrying metal layer, wherein the sensing bitline metal layer does not carry current.