Dual-Metal GAA Gate Patterning for Threshold Voltage Stability
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Solution Overview
Problem
As gate geometries shrink in gate-all-around (GAA) transistors, there is less space for work-function metals, leading to patterning challenges that affect threshold voltage reliability and process variability, including issues like undesired Vt shifts and strain loss due to insufficiently precise patterning of dual-metal gates.
Innovation Solution
A dual-metal gate structure is implemented using a template material and selective deposition of work-function (WF) metals, where the first WF metal is deposited thickly on a template to set the threshold voltage and shield the channel, and the second WF metal is conformally deposited to prevent shine-through, reducing the need for lithographic operations and preserving strain engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional dual-metal gate patterning is used with multiple lithographic operations, then threshold voltage can be set, but patterning precision requirements increase and process variability worsens
Solution Approach 1:
The gate structure is segmented into multiple metal layers (first WF metal layer and second WF metal layer) with different functions. The first layer provides threshold voltage setting while the second layer provides shielding, dividing the原本 single patterning step into selective deposition processes that reduce precision requirements for each individual layer.
Solution Approach 2:
The first work-function metal layer is deposited and configured in advance to establish the desired threshold voltage. This preliminary action allows the threshold voltage to be set before the second metal layer is added, enabling subsequent layers to focus on shielding without affecting Vt, thereby reducing overall patterning precision requirements.
2Productivity
If gate geometries are shrunk to enable scaling, then device density improves, but space for work-function metals decreases and patterning challenges increase
Solution Approach 1:
The solution moves from planar patterning to vertical stacking by implementing multiple WF metal layers at different heights. The first WF metal layer is positioned closer to the channel for Vt control, while the second layer is positioned above for shielding. This vertical dimensionality change allows both functions to coexist in shrunk gate geometries without increasing lateral patterning complexity.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the first and second WF metal layers. This intermediary layer provides electrical isolation and mechanical support, enabling the stacked configuration to function properly in scaled devices without requiring complex lateral patterning to separate the metal regions.
3Reliability
If the second WF metal is deposited closely to the active gate or in excessive quantities, then shielding is improved, but Vt shifts occur due to shine-through
Solution Approach 1:
The patent uses a template gate structure (such as a polysilicon gate) as a patterned substrate that guides the conformal deposition of the first WF metal layer. This template copying approach ensures uniform thickness and precise spatial distribution of the first metal layer, preventing excessive deposition that would cause shine-through to the second layer while maintaining effective shielding.
4Ease of manufacture
If patterning operations are performed on WF metals, then gate material can be removed, but the retained WF metal degrades (oxidizes) and Vt shifts
Solution Approach 1:
Instead of removing patterned WF metal through etching (which causes degradation), the patent inverts the approach by adding a second WF metal layer on top of the first. This additive approach achieves the desired gate structure configuration without subjecting the first WF metal layer to degrading patterning operations, thereby maintaining Vt stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves process capability for gate scaling, reduces process variability, and enhances device reliability by setting desired threshold voltages without patterning-related shifts, enabling continued device geometry shrinking and efficient Vt-shifting solutions.
Implementation Method 1
a first work-function (WF) gate metal that selectively deposits on the template material
Implementation Method 2
a second WF gate metal that is conformally deposited to set a complementary Vt
Data Source
AI summary
Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.