Dual Metal Gate CMOS Work Function Tuning via Ion Implantation
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Solution Overview
Problem
The integration of dual metal gates and dual high-k dielectrics in CMOS devices is complex, leading to poor controllability and high manufacturing costs, particularly due to Fermi level pinning effects and the need for different work functions in N-type and P-type MOS devices, which complicates the achievement of appropriate threshold voltages.
Innovation Solution
A method involving the formation of interfacial oxide and high-k gate dielectric layers, followed by metal gate deposition and ion implantation with different dopants for N-type and P-type devices, allowing metal ions to accumulate at interfaces and adjust work functions through high-temperature annealing, simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional polysilicon gate is used with high-k gate dielectric layer, then the high-k layer provides larger physical thickness at same EOT reducing tunneling current, but Fermi level pinning effects occur leading to serious compatibility issues
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional polysilicon to metal materials (such as TiN, TaN, MoN, W, Pt, Ir). This material substitution fundamentally alters the electrical properties at the gate-dielectric interface, eliminating Fermi level pinning effects while preserving the high-k dielectric's ability to reduce tunneling current through its large physical thickness at equivalent oxide thickness.
Solution Approach 2:
The patent employs composite material structures combining metal gate electrodes with high-k gate dielectric layers (such as HfO2, HfSiO, HfSiON, HfAlO, HfAlON). This composite approach leverages the advantageous properties of both materials: the metal gate provides appropriate work function and eliminates Fermi level pinning, while the high-k dielectric provides electrical isolation and reduces tunneling current.
2Reliability
If dual metal gates and dual high-k gate dielectrics are integrated for NMOS and PMOS devices, then appropriate threshold voltages can be achieved, but the process becomes very complicated with poor controllability and high manufacturing cost
Solution Approach 1:
The patent applies local quality by selectively doping metal gate regions with different dopant types (P-type for PMOS, N-type for NMOS) to achieve device-specific work functions. This localized modification allows each transistor type to have optimized electrical characteristics while using the same base metal gate material and high-k dielectric structure, thereby simplifying the overall integration process.
Solution Approach 2:
The patent segments the metal gate structure into region-specific doped zones within a unified gate stack architecture. By dividing the gate into selectively doped regions corresponding to NMOS and PMOS devices, the patent achieves different threshold voltages for each device type without requiring separate gate fabrication processes, thus reducing complexity.
3Reliability
If multiple deposition, photolithography, and etching steps are performed for dual metal gates, then respective suitable metal gates can be formed for NMOS and PMOS, but manufacturing cost increases and mass production is hindered
Solution Approach 1:
The patent merges the fabrication of dual metal gates into a single integrated process flow. By forming both NMOS and PMOS metal gates simultaneously using one deposition step followed by selective doping and a unified etching process, the patent eliminates the need for separate deposition and photolithography steps for each gate type, thereby reducing manufacturing cost and facilitating mass production.
Solution Approach 2:
The patent employs a universal metal gate material system that serves both NMOS and PMOS devices. The same base metal material (e.g., TiN, TaN) is used for both device types, with differentiation achieved through selective doping rather than through separate material deposition processes. This universal approach simplifies manufacturing while maintaining device-specific performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively adjusts the work functions of NMOS and PMOS devices, achieving appropriate low threshold voltages while simplifying the integration process and reducing manufacturing costs, making it compatible with CMOS technology for mass production.
Implementation Method 1
doping the metal nitride gate by metal ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device
Implementation Method 2
forming an interfacial oxide layer of SiOx or SiON after formation of a device isolation by rapid thermal annealing at a temperature of 600-800° C. for 20-120 s
Implementation Method 3
performing a thermal annealing at a temperature of 600-1050° C. for 2-30 s, wherein in the course when the dopants in the source/drain regions are activated
Implementation Method 4
a TiN gate is deposited by a physical vapor deposition (PVD) process
Implementation Method 5
depositing a poly-silicon layer and a hard mask by a low pressure chemical vapor deposition (CVD) process
Data Source
AI summary
The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or oxynitride layer by rapid thermal oxidation; forming a high-k gate dielectric layer on the ultra-thin interfacial oxide layer by physical vapor deposition; performing a rapid thermal annealing after the deposition of the high-k; depositing a metal nitride gate by physical vapor deposition; doping the metal nitride gate by ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device, with a photoresist layer as a mask; depositing a polysilicon layer and a hard mask by a low pressure CVD process, and then performing photolithography process and etching the hard mask; removing the photoresist, and then etching the polysilicon layer/the metal gate/the high-k dielectric layer sequentially to provide a metal gate stack; forming a first spacer, and performing ion implantation with a low energy and a large angle for source/drain extensions; forming a second spacer, and performing ion implantation for source/drain regions; performing a thermal annealing so as to adjust of the metal gate work functions for the NMOS and PMOS devices, respectively, in the course when the dopants in the source/drain regions are activated.