Dual Metal Gate Work Function Layer Selective Removal
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Solution Overview
Problem
Conventional poly-silicon gates in semiconductor devices face issues like boron penetration and depletion, leading to reduced gate capacitance and performance, prompting the use of high-k gate dielectric layers, which complicates the manufacturing process and requires precise control for dual metal gate structures.
Innovation Solution
A semiconductor structure and method involving two material layers with different etching selectivity as hard masks, allowing the etching process for removing the work function layer to be performed only once, thereby simplifying the manufacturing process and reducing N/P boundary issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual metal gate structure is used to replace poly-silicon gates, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies local quality by using a single work function layer material that is selectively removed in different regions to achieve different gate characteristics. The work function layer is entirely removed in first device regions (NMOS) and partially retained in second device regions (PMOS), creating region-specific functionality from a uniform initial structure. This eliminates the need for separate work function metal layers for different device types, simplifying the manufacturing process while maintaining dual metal gate performance benefits.
2Manufacturing precision
If multiple etching processes are used to remove work function layer, then precise control is achieved, but manufacturing time increases
Solution Approach 1:
The patent merges multiple etching operations into a single etching process by using a unified mask structure (first material layer and second material layer) that defines both complete removal regions and partial retention regions. The first material layer is removed entirely in first device regions while being partially retained in second device regions, achieving both complete and partial work function layer removal in one step. This eliminates the need for separate etching processes that would otherwise be required to achieve different removal patterns.
Solution Approach 2:
The patent introduces material layers (first material layer and second material layer) as intermediary masking structures that control the etching process. These intermediary layers serve as mediators between the etching chemistry and the work function layer, enabling precise spatial control of work function layer removal without requiring multiple etching steps. The intermediaries translate a single etching operation into region-specific outcomes through their selective presence and removal characteristics.
3Ease of manufacture
If conventional poly-silicon gates are used, then manufacturing process is simple, but device performance deteriorates due to boron penetration and depletion
Solution Approach 1:
The patent changes the material parameter of the gate structure by replacing poly-silicon with a high-k dielectric layer combined with a work function layer. This parameter change (material composition) enables better electrical characteristics and eliminates boron penetration issues while maintaining manufacturing simplicity through the use of conformal deposition techniques and a single work function layer that can be selectively removed or retained based on device type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and time of the manufacturing process while maintaining the performance of semiconductor devices by ensuring precise control over the work function layer removal, enhancing the yield and reducing costs.
Implementation Method 1
using two material layers with different etching selectivity as hard masks
Data Source
AI summary
The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.