Dual Metal Gate Structures for Low Resistance Semiconductor Devices
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing gate resistance for both short channel and long channel devices, particularly due to the high resistivity of titanium nitride barrier layers and the scaling down of gate conductor volumes, which affects performance and power consumption.
Innovation Solution
The implementation of a dual gate structure with different metal gate conductor layers, where the first gate structure has a shorter width and is made of a higher resistivity metal like cobalt, and the second gate structure has a longer width and is made of a lower resistivity metal like tungsten, with a conductive barrier layer arranged next to the side and bottom surfaces of the tungsten gate conductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a titanium nitride barrier layer is used between the tungsten gate conductor layer and the work function metal layer, then the gate structure provides adequate barrier protection, but the gate resistance increases due to the high resistivity of titanium nitride
Solution Approach 1:
The gate conductor layer is segmented into multiple metal layers with different materials (e.g., tungsten and cobalt) and different thicknesses. The lower layer (closer to the barrier) has higher resistivity while the upper layer has lower resistivity, creating a composite structure that balances barrier protection and resistance reduction.
Solution Approach 2:
Different regions of the gate conductor have different material compositions optimized for their specific functions. The lower gate conductor layer near the barrier uses materials with higher resistivity for adequate spacing and protection, while the upper layer uses low-resistivity materials to minimize overall gate resistance.
2Volume of moving object
If the gate conductor volume is reduced to scale down device features, then the device size decreases, but the gate resistance increases due to smaller conductor volume
Solution Approach 1:
The gate conductor is constructed as a composite of multiple metal layers with different electrical properties. By combining materials like tungsten (lower resistivity) and cobalt (higher resistivity) in specific thickness ratios, the composite structure achieves lower overall resistance than a single-material conductor of the same reduced volume would provide.
Solution Approach 2:
The resistivity parameter of the gate conductor is optimized by changing the material composition and thickness distribution of multiple layers. The lower layer uses materials with higher resistivity while the upper layer uses materials with lower resistivity, creating a gradient structure that minimizes overall resistance despite reduced volume.
3Manufacturing precision
If different metal gate conductor layers with different resistivities are used in first and second gate structures, then the gate resistance is optimized for both short channel and long channel devices, but the fabrication process becomes more complex
Solution Approach 1:
The gate conductor is divided into multiple layers that can be deposited sequentially using standard CVD processes. Each layer is formed in a separate deposition step, allowing independent optimization of material composition and thickness for each layer while using conventional fabrication equipment and processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with significantly reduced gate resistance, leading to faster speed and lower power consumption for both short channel and long channel devices, while also simplifying the fabrication process without the need for additional photolithographic masks.
Implementation Method 1
Chemical vapor deposition (CVD) process is typically used to deposit the tungsten metal
Data Source
AI summary
A structure comprises a substrate and a first gate structure and a second gate structure in a dielectric layer over the substrate. The first and second gate structures having a width, the width of the first gate structure is shorter than the width of the second gate structure. The first gate structure comprises a first gate conductor layer and the second gate structure comprises a second gate conductor layer. The first gate conductor layer is made of a different metal from the second gate conductor layer.