Dual-metal via sidewall etching for TDDB mitigation
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Solution Overview
Problem
The challenge in integrated circuit (IC) fabrication is the reliability issue due to poor overlay and misalignment between trench and vias, leading to time-dependent dielectric breakdown (TDDB), which is exacerbated by increasing electrical fields as IC footprints reduce.
Innovation Solution
The implementation of dual-metal vias, where a first metal lines the sidewalls and base, and a second metal forms the via core, allowing selective etching of the sidewall to increase the distance between interconnect elements, thereby reducing electrical field strength and mitigating TDDB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC footprint is reduced to increase integration density, then productivity and integration density are improved, but electrical field strength increases causing TDDB reliability issues
Solution Approach 1:
The via structure is segmented into two separate metal components: a first metal forming the via sidewalls and base, and a second metal forming the via core. This segmentation allows independent optimization of each metal's properties and positions, enabling increased spacing between conductive elements to reduce electrical field strength and mitigate TDDB while maintaining high integration density
Solution Approach 2:
Different metals are used for different parts of the via structure based on local requirements. The first metal (e.g., tungsten) provides mechanical strength and etch selectivity for the sidewalls, while the second metal (e.g., copper) provides high conductivity for the core. This local quality differentiation enables optimized electrical field distribution and reduced TDDB in high-density interconnect structures
2Reliability
If distance between conductive elements is increased to reduce electrical field strength, then TDDB reliability is improved, but area consumption increases
Solution Approach 1:
The dual-metal via structure utilizes vertical dimensionality by forming the first metal as sidewalls and the second metal as a core within the same via footprint. This three-dimensional configuration increases the effective distance between conductive elements in the horizontal plane without increasing the lateral area, thereby reducing electrical field strength and mitigating TDDB while maintaining high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces TDDB failure by increasing the distance between conductive elements, maintaining tolerable electrical field levels and improving IC reliability as IC footprints continue to shrink.
Implementation Method 1
etching a portion of the first dual-metal via to increase the distance separating the first dual-metal via from a second dual-metal via
Data Source
AI summary
An integrated circuit (IC) structure includes a dielectric layer extending along a first axis to define a length and a second axis orthogonal to the first axis to define a width. A dual-metal via is embedded in the dielectric layer. The dual-metal via includes via sidewalls surrounding a via core. An electrically conductive line extends along the first axis and on an upper surface of the dual-metal via. A side portion of the via core is co-planar with a sidewall of the electrically conductive line.