Dual Metal Wrap-Around Contacts for Low-Resistance FinFETs
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving low-resistivity dual metal wrap-around contacts, particularly in aggressively scaled devices like FinFETs, where tight control of parasitic capacitance and optimized metal-semiconductor contact resistance are critical.
Innovation Solution
The implementation of dual metal wrap-around contacts in semiconductor devices involves growing n-type and p-type doped epitaxial semiconductor materials on raised features in NFET and PFET regions, respectively, and forming contact metals on both upward and downward facing surfaces, with the option for the contact metals to be the same or different.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual metal wrap-around contacts are implemented to reduce contact resistance, then contact resistance is improved, but device complexity increases
Solution Approach 1:
The contact structure is divided into two separate metal layers (first contact metal and second contact metal) with different functions. The first contact metal provides low-resistivity contact to the semiconductor substrate, while the second contact metal provides wrap-around coverage. This segmentation allows each layer to be optimized for its specific function, reducing overall contact resistance while maintaining manageable complexity through functional division.
Solution Approach 2:
The patent implements a nested structure where the first contact metal is positioned within or alongside the second contact metal structure. The epitaxial semiconductor material grows around the first contact metal, and the second contact metal wraps around this combined structure. This nesting approach maximizes contact area and reduces spreading resistance by utilizing three-dimensional space efficiently, while the integrated growth process helps manage manufacturing complexity.
2Reliability
If wrap-around contact structure is used to increase contact area, then spreading resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The first contact metal is deposited and patterned before the epitaxial semiconductor material growth. This preliminary positioning establishes a precise template that guides the subsequent epitaxial growth to wrap around the contact metal in a controlled manner. By pre-defining the contact metal structure, the patent reduces the precision requirements for the final wrap-around formation, as the epitaxial growth naturally follows the pre-established template.
Solution Approach 2:
The epitaxial semiconductor material self-organizes and wraps around the first contact metal structure during the growth process. This self-service mechanism reduces the need for complex external patterning steps to achieve the wrap-around geometry. The material's inherent growth properties drive the formation of the desired three-dimensional contact structure, thereby reducing manufacturing precision requirements while still achieving low spreading resistance through increased contact area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances contact area and reduces spreading resistance in FinFET structures, thereby improving the performance of aggressively scaled semiconductor devices by optimizing contact resistance and controlling parasitic capacitance.
Implementation Method 1
growing a first n-type doped epitaxial semiconductor material on the first raised feature
Data Source
AI summary
A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.