Dual Metallization Interconnects for Void-Free Narrow Trenches
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Solution Overview
Problem
Copper interconnects in semiconductor fabrication are prone to void formation as they are scaled down, leading to increased electrical resistance and RC delay due to issues with diffusion barrier layers and seed layer coverage in narrow trenches and via openings.
Innovation Solution
Using metallic materials like cobalt or ruthenium, which do not require thick diffusion barrier layers or seed layers, to fill narrow trenches and via openings, allowing for void-free formation of metallic interconnects by employing thin liner layers as adhesion and wetting layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper material is used to form BEOL interconnects, then electrical resistance is reduced and conduction is improved, but void formation occurs during copper filling of narrow trenches
Solution Approach 1:
The patent applies different metallic materials to different regions based on trench width: cobalt or ruthenium for narrow trenches (where void formation occurs) and copper for wider trenches (where copper filling works well). This local differentiation resolves the contradiction by ensuring each region uses the material best suited to its specific dimensions, eliminating voids in narrow areas while maintaining the low resistance benefits of copper in wider areas.
2Productivity
If copper interconnect structures are scaled down with smaller widths and pitches, then interconnect density is increased, but void formation becomes more prone
Solution Approach 1:
The invention implements a width-based material selection strategy where the metallic material is locally optimized according to trench dimensions. Narrow trenches (with smaller widths and pitches) use cobalt or ruthenium which do not suffer from void formation during deposition, while wider trenches use copper. This enables high interconnect density through scaling while maintaining reliability by avoiding voids in the most critical narrow features.
3Ease of manufacture
If thick diffusion barrier layers and seed layers are used for copper filling, then copper deposition is enabled, but void formation increases in narrow trenches
Solution Approach 1:
The patent changes the material parameter (metallic material type) based on trench width to avoid the void formation issue. For narrow trenches, it uses cobalt or ruthenium which can be deposited with thin liner layers (0.5-2 nm) without requiring thick diffusion barrier and seed layers. This parameter change eliminates the root cause of void formation while still enabling effective interconnect formation in narrow features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates void formation in interconnects, reducing electrical resistance and RC delay, and enables the fabrication of reliable metallic interconnect structures with improved performance.
Implementation Method 1
depositing a first layer of liner material to form a first liner layer on sidewall and bottom surfaces of the first and second trench openings
Implementation Method 2
employing thin liner layers as adhesion and wetting layers
Implementation Method 3
depositing a first layer of metallic material to fill the first trench opening with metallic material
Implementation Method 4
depositing a second layer of metallic material to fill the second trench opening with metallic material
Implementation Method 5
performing an etch process to remove a portion of the first layer of metallic material within the second trench opening, while the etch protection layer protects the metallic material within the first trench opening from being etched during the etch process
Data Source
AI summary
Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.


