Dual Microprocessor Access Control for Legacy Signal Timing

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Solution Overview

Problem

Legacy access control systems face challenges with high timing accuracy requirements for signal transmission, limited range due to dedicated wiring, and inefficiencies with low-power microcontrollers, leading to errors and increased costs in upgrading or retrofitting existing infrastructure.

Innovation Solution

A microcontroller system comprising a primary microprocessor for digital communications and a secondary microprocessor dedicated to signal timing, intercepting and transforming legacy signals for secure transmission and reception, enabling interoperability with digital backend systems and extending access control functionality without the need for high-power CPUs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high-power CPUs are used to achieve high timing accuracy for legacy signal transmission, then timing accuracy is improved, but device complexity and cost increase

Engineering Contradiction:
Improvetiming accuracyVSAvoidmicroprocessor complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system divides the microprocessor functionality into two separate components: a primary microprocessor for general digital communications and a secondary microprocessor specifically dedicated to signal timing and legacy protocol handling. This segmentation allows the secondary microprocessor to be optimized for timing-critical operations without requiring the entire system to use high-power CPUs, thus improving timing accuracy while controlling device complexity and cost.

Inventive Principle:
Principle #1Segmentation

2Reliability

If dedicated wiring is used for legacy access control systems, then reliability of signal transmission is improved, but installation cost and device complexity increase

Engineering Contradiction:
Improvesignal transmission reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary access control reader that acts as a bridge between legacy access control systems and modern wireless infrastructure. The reader includes a receiver for legacy protocols and a transmitter for wireless communications, enabling legacy systems to communicate over wireless networks without requiring dedicated wiring throughout the building, thus reducing installation complexity while maintaining reliable signal transmission through the intermediary device.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If wireless protocols with short range are used to eliminate wiring, then ease of installation is improved, but operating range deteriorates

Engineering Contradiction:
Improveinstallation easeVSAvoidoperating distance
Core Design Contradiction:
Ease of manufactureVSLength of moving object

Solution Approach 1:

The system merges multiple communication capabilities into a single access control reader: legacy protocol reception (Wiegand, OSDP), modern wireless communication (Wi-Fi, Bluetooth, cellular), and optional long-range radio protocols. This combination allows the system to eliminate dedicated wiring while achieving extended operating ranges beyond the limitations of short-range wireless protocols alone, as the reader can use appropriate communication methods based on distance requirements.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20230353551A1Access control system
Publication Date: 2023.11.02 MEDIXSAFE INC
  • US20230353551A1 patent drawing
  • US20230353551A1 patent drawing
  • US20230353551A1 patent drawing

AI summary

A device is described that includes a first microprocessor configured for interfacing with a digital access control backend, and a second microprocessor configured for dedicated communications with an access control manager device backend. The first microprocessor is a master device that controls the operation of the second microprocessor as a secondary device. The proposed device is configured for operation of the first microprocessor and the second microprocessor at low clock speeds and to maintain a hash segregation between locally received data sets and data sets transmitted to an external authentication system.