Dual-Microprocessor Lockstep With Time-Counter Instruction Dispatch
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Solution Overview
Problem
The challenge of implementing dual-core lock step in microprocessors for automotive applications is the high cost and complexity of duplicating cores, which is exacerbated by the increasing complexity and size of microprocessors, necessitating a more efficient and scalable architecture that meets functional safety requirements.
Innovation Solution
A register scoreboard with a time counter is used to statically dispatch instructions based on a time count, ensuring that instructions are executed at preset times, and a time counter increments periodically to schedule execution, allowing for efficient resource utilization and error detection between dual cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-core lock step is implemented to ensure functional safety, then reliability is improved, but device complexity increases due to core duplication
Solution Approach 1:
The patent merges the safety verification function into a single core by implementing a time counter and static dispatching mechanism that tracks and verifies instruction execution timing. Instead of duplicating entire cores for safety verification, the system combines the primary execution core with a time-counting and verification subsystem that monitors instruction dispatch timing, thereby achieving dual-core lockstep functionality with reduced hardware complexity.
Solution Approach 2:
The time counter and static dispatching unit serve multiple functions: they track instruction execution timing, verify functional safety by ensuring identical execution between cores, and optimize resource utilization by scheduling instructions at preset times. This multi-functional component replaces what would traditionally require separate safety verification hardware, reducing overall device complexity while maintaining reliability.
2Productivity
If microprocessor complexity increases to meet performance requirements, then productivity is improved, but device complexity increases making lock step more costly
Solution Approach 1:
The patent segments the microprocessor into distinct functional units: a primary execution core for high-performance processing, a time counter for tracking execution cycles, and a static dispatching unit for instruction scheduling. This segmentation allows the complex processing functions to be isolated in the execution core while the simpler time-counting and verification functions are handled by dedicated but less complex units, making the overall system more manageable and cost-effective.
Solution Approach 2:
The static dispatching unit performs preliminary actions by pre-scheduling instructions at preset times based on time count values. Instructions are dispatched in advance to functional units based on predicted execution timing, allowing the system to optimize resource utilization before execution begins. This preliminary scheduling reduces the complexity of real-time coordination that would be required in a fully dynamic system.
Data Source
AI summary
A processing system includes a time counter, a block of memory and register files, a first processor core and a second processor core, and wherein the processor core includes a register scoreboard and provides a method for statically dispatching instructions with preset execution times based on a write time of a register in the register scoreboard and the time counter provided to an execution pipeline. The processing system also includes method for comparing and validating the functional safety of the processor cores.